Wednesday, March 31, 2010

Statistics for March 2010

Thank you all for being interested in and supportive of MEP development.

Here are some statistics for March

Average daily number of RSS feed subscribers: 31
Number of subscribers on the mailing list: 37
Unique visitors in March: 744

6.54GB were downloaded from the site for December. This is well within our bandwidth allocation. We are well within our disk space quota as well. No service disruptions were reported for March.

The most popular items were the Xilinx manuals, the SBMS Newsletter from March 2010, The High-Speed Multimedia notes from February, and the Xilinx Integrated Software Environment.

Many visitors to the site were from the USA. However, Hong Kong was the most frequent visitor, and India and Australia ranked high as well.

Please let me know what would make the site, feed, and list more useful and helpful and I'll do all that I can to achieve it. Since so many of us are spread out so far, a useful site and tool set is important in order to communicate effectively.

Updated MEP Software Page

I added a description of how to obtain our FPGA software tool (free) from Xilinx.

Tuesday, March 30, 2010

FPGA 1.1 drawing and questions

Here's today's sketch of the FPGA. It now has stuff coming out the other side!

One of the comments was to go ahead and connect the FGPA to a processor, like the TI OMAP in the Beagleboard, directly. I'm assuming that it's connected directly in a large parallel interface to memory. There's a lot of available pins on the TI OMAP.

Another FPGA output could be IPv6 and IPv4 packets.
-Michelle W5NYV

weekly plan 29 March - 2 Aril 2010 "Costas Loop in VHDL, IQ Demodulator Evaluation Boards"

Greetings everyone,

Here's my plan for the week.

1. (Begin to) implement a Costas Loop in VHDL. Anyone out there already done this?
2. Set up the website for sharing VHDL source code. I noticed several VHDL projects on sourceforge. Perhaps when we have some code to share, starting a sourceforge project area would be a good idea.
3. Fix the twitter badge belonging to one of the three people that have a twitter badge on the MEP homepage. If you use twitter, and would like to be on the home page, just let me know and I'll put you there.
4. Decide whether or not to order an evaluation board for an IQ demodulator. I'm looking at something like a Skyworks evaluation board. They come with the demodulator soldered down, but you place the other parts to get the right frequency range. There's a parts list for 3200-3900MHz, which just happens to include one of our intended bands.

Here's the rather unrevealing product webpage:

My questions are "Are there any other cheaper alternatives to this evaluation board?" and "Does anyone have anything like this lying around that we could borrow?" Let us know. I might be able to get a lot of use out of this evaluation board in the local microwave scene as a loaner or building block, but $199 is expensive enough to justify talking about it and looking around some more.

If you have the time and inclination to help confirm or contradict any of these ideas, please do! It would be greatly appreciated.

More soon,
-Michelle W5NYV

Friday, March 26, 2010

MEP receiver proposal - with FPGA (very high level beginning sketch)

Here's the basic idea. More to come. Please let me know what you think.

Weekly Report 22-26 March 2010: FPGA updates and a ham radio modem design

Here is a weekly report for 22-26 March 2010.
I started reading a book about reconfigurable computing.
This type of computing uses FPGAs in order to perform computations. The CPU chooses from a variety of configurations in order to set up an FPGA to solve a particular problem or set of problems. One has to figure out if the overhead of reconfiguring the FPGAs is worth the time saved by dedicated hardware (the designs in the FPGAs). It's made for some interesting reading, that's for sure. I got the book thinking it would be about general FPGA usage, but reconfigurable computing is somewhat of a specialized field that uses FPGAs as a tool to get the job done. "Real" reconfigurable computers have been designed and built and used successfully, but the market just isn't there for most companies that have tried to build reconfigurable computers as a commercial endeavor.
Now, there isn't that much here that affects MEP. Our computations are not (I don't think) difficult or wide-ranging enough to have to build a configuration management processor and swap out configurations. However, the chapter on learning VHDL is useful, and the compute vs. dataflow modeling explanations were illuminating and (to me) fun to read.

The free version of the older Integrated Software Environment (version 10.1 of the ISE) for Xilinx FPGA development did not support the larger Virtex II FPGA in the XtremeDSP Development kit. I downloaded the current free version of the ISE, and as expected, it didn't support families of FPGAs earlier than the Virtex IV.
I updated it from (free) version 11.1 to (free) version 11.5, which added the very latest Spartan 6 family to the ISE. While there isn't any target hardware doing it this way, it does allow us to develop for the latest versions of the Xilinx Spartan chip. I packed up the development station that we were loaned and will deliver it back this weekend with our thanks.
To participate in MEP FPGA design, then download the 11.1 Webpack ISE from Xilinx and update it. When you update it, there will be one DSP-related thing that you will not be able to include. Uncheck that box, and you will be able to update to 11.5 for free.
Here is a page of Xilinx ISE 11 tutorials.
I decided to look around for other amateur radio FPGA projects and found some mention of FPGA in amateur radio in a TAPR newsletter and found a modem project by a ham, which was implemented using Xilinx FPGAs. Summary is below.
Ham Radio Systems On A Chip by Steve Bragg KA9MVA from TAPR Packet Status Register #102 located at
"...the latest field programmable gate arrays (FPGAs) pack enough digital hardware to be called SoCs in their own right. Falling prices, exponentially increasing gate counts, and low-cost design software are converging to make FPGAs the right technology for emerging ham radio systems-on-a-chip."
"A ham radio SoC includes signal processing 'blocks' for the most popular modes of ham radio: analog and digital voice, ATV/SSTV, packet, data and APRS®. Vocoders and decoders, such as that developed by G4GUO and G4JNT3 can be included. Audio processing (such as speech processing, VOX and stereo synthesis) can be in the SoC. Packet engines and TNCs should also be included.
An example of an FPGA-based TNC device is Nico Palermo, IV3NWV's YAM modem4, released in 1997. The TNC-like YAM was based on the Xilinx XC5200-series FPGA, the equivalent about 3,000 gates5. IV3NWV's clever coding crammed both 1200-bit/s AFSK and 9600-bit/s G3RUH modems into a small Xilinx FPGA. Today, the equivalent of the YAM, and much more besides, can be incorporated into a ham radio SoC."
The YAM (Yet Another Modem) Modem can be read about here:
Three configuration files can be downloaded by email request. The "features" section discusses the details of the modem.

Wednesday, March 17, 2010


We walked through the short tutorial, which makes a simple counter and then provides a testbench waveform to wiggle bits, and found out something important.

The Xilinx ISE 10.1 free "webpack" doesn't target the FPGA in the XtremeDSP development kit. The free version tops out at the Virtex II version 400. Ours is a Virtex II version 3000.

Next step: Download the Xilinx ISE 11 free "webpack", and see if it has supported device limits. Version 11 doesn't' support the older Virtex II chip, but it can target the modern current FPGAs. I'll write more about what I find out in a bit.


Monday, March 15, 2010

Xilinx webinar notes, FPGA station

Here's the notes I took during the Xilinx "Achieving 1000 GMACs of DSP Performance with Xilinx FPGAs" webinar.

A GMAC is Giga Multiply-Accumulate Operations Per Second. This is somewhat similar to the measurement of "operations per second" for processors, and provides one way to compare and contrast circuitry that is capable of doing multiply-accumulates.

The thing that got my attention was what I sketched out on page 4, which is how many more MACs FPGAs are currently doing (with the Virtex and Spartan 6 series) when compared to "conventional" DSPs.

I'm reading a book on reconfigurable computing, which is an area of computing that has "settled" for using FPGAs. A "true" reconfigurable computer isn't exactly modeled or enabled by an FPGA, but since FPGAs are a commodity device, the field of reconfigurable computing seems to have coalesced around them. The book essentially echoes what the "sellinars" say. FPGAs are a "for real" DSP device.

What I got from this is that using FPGAs for MEP is not misguided. :+)

Anyone coming along with another development station? I've read through the short tutorial for using Xilinx ISE 10.1 and might actually be able to show off a "hello world" application sometime today.

-Michelle W5NYV

Potestatem obscuri lateris nescis.

Thursday, March 11, 2010

Xilinx ISE 10.1 Design Suite Software

Xilinx (Integrated Software Environment) ISE 10.1 Design Suite Software, which allows you to take the VHDL code and turn it into a bit file, which is then loaded into an FPGA to program it for a particular set of tasks... is being downloaded as I type. Exciting stuff!

You can get the ISE 10.1 software free from the Xilinx web site. The current version is 11, but a link in the upper right hand of the Downloads Entitlement Page reads "Looking to register 10.1 or earlier software products?"

If you click that, you can download ISE WebPACK 10.1 as a free download.

This, as best I can tell, supports the Virtex II. The current version of the ISE picks up at Virtex IV.

Here's a document from Xilinx that might be helpful in finding documentation about ISE 10.1.

Notice that you can do simulations with this software.

More soon,-Michelle W5NYV

Wednesday, March 10, 2010

San Diego Microwave Group meeting announcement

Hello San Diego Microwavers,

Monday evening, March 15th is the date for this month's meeting of the San Diego Microwave Group.

Location is Kerry Banke's home at 6026 Poppy Street in La Mesa and starting time is 7:00 PM.

Kerry (N6IZW) announced the technical topic will be on Phase Lock Loop (PLL) Local Oscillator circuits and performance.

Bring your latest show and tell gear, and any unidentified microwave objects. We will see if anyone can help you figure out what they do. The meeting will start in Kerry's garage workshop where the test equipment is available.

Hope to see you there!!
73s from Ed Munn, W6OYJ

Tuesday, March 9, 2010

HSMM Webinar Notes 6 Feb 2010

Here's a link to my livescribe notes from the HSMM webinar held 6 Feb 2010.
-Michelle W5NYV

Potestatem obscuri lateris nescis.

Thursday, March 4, 2010

San Bernardino Microwave Society meeting tonight in Corona, CA

A couple of us will be at the San Bernardino Microwave Society meeting tonight at 7:00pm in Corona, CA. Please come and check out the meeting if you're able - tonight's presentation is described below:

"At the 4 March 2010 SBMS meeting the "Tech Talk" will be Tony, KC6QHP talking about a wide range of
activities to support the construction of a 47 GHz radio. Including; EDM machining, making waveguide switches,
embedded microcontroller for TR switching, building a suitable tripod head, acquisition of hard to get parts (caps,
wire bonding wire, substrates, chips, epoxies, etc.) putting together circuits with MMICs, interfacing to and from
bare die MMICs, etc. The SBMS meets at the American Legion Hall 1024 Main Street (south of the 91 freeway) in
Corona, CA at 1900 hours local time on the first Thursday of each month. Check out the SBMS web site at"

Link to this month's SBMS Newsletter here:

-Michelle W5NYV

Potestatem obscuri lateris nescis.