tag:blogger.com,1999:blog-4102882222358171482024-03-05T16:29:49.103-08:00Microwave Engineering ProjectA system for amateur radio.Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.comBlogger150125tag:blogger.com,1999:blog-410288222235817148.post-90974649587200674012012-06-10T10:34:00.001-07:002012-06-10T10:34:04.603-07:00LinkedIn Password Reset Notification<table border="0" width="550" cellpadding="0" cellspacing="0" style="max-width:550px; border-top:4px solid #39C; font: 12px arial, sans-serif; margin: 0 auto;"><tr><td> <h1 style="color: #000; font: bold 23px arial; margin:5px 0;" >LinkedIn</h1> <p style="margin-bottom: 6pt;">Hi Jeffrey,</p> <p style="margin-bottom: 6pt;">Your LinkedIn password has been reset successfully.</p> <p style="margin-bottom: 6pt;">Thank you,</p> <p>The LinkedIn Team</p> <table border="0" cellspacing="0" cellpadding="0" style="font-family:Arial;" width="100%"> <tr><td><table width="1" border="0" cellspacing="0" cellpadding="0"><tr><td><div style="height:10px;font-size:10px;line-height:10px;"> </div></td></tr></table></td></tr> <tr> <td align="left" style="font-size:11px; font-family:Arial,sans-serif; color:#999999;"> This email was intended for Jeffrey Pawlan. <a style="color: #006699" href="http://www.linkedin.com/e/8eya3p-h3ae73f5-2c/plh/http%3A%2F%2Fhelp%2Elinkedin%2Ecom%2Fapp%2Fanswers%2Fdetail%2Fa_id%2F4788/-GXI/?hs=false&tok=3REx2IIwE-Dlg1">Learn why we included this</a>. © 2012, LinkedIn Corporation. 2029 Stierlin Ct. Mountain View, CA 94043, USA </td> </tr> <tr><td><table width="1" border="0" cellspacing="0" cellpadding="0"><tr><td><div style="height:10px;font-size:10px;line-height:10px;"> </div></td></tr></table></td></tr> </table> Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-70241921054572446432012-01-27T12:40:00.001-08:002012-01-27T12:40:16.120-08:00Heads-up Display Proposal for GNU Radio (and MEP)Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com1tag:blogger.com,1999:blog-410288222235817148.post-42004347876697954692011-08-28T09:14:00.000-07:002011-08-28T09:14:03.948-07:00Six-PortsPaper appearing in The Proceedings of Microwave Update 2011. It's about the basics of six-port theory, with an explanation of six-ports as modulator and demodulator.Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-24956877199757337412011-08-27T19:19:00.001-07:002011-08-27T19:19:45.421-07:00Six-port article for MUD<div style="color:#000; background-color:#fff; font-family:times new roman, new york, times, serif;font-size:12pt"><div><meta http-equiv="x-dns-prefetch-control" content="off"></div><div id="yiv1813008296"><div style="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); font-size: 12pt; font-family: 'times new roman', 'new york', times, serif; "><div id="yiv1813008296yui_3_2_0_17_131440696601448"><span id="yiv1813008296yui_3_2_0_17_131440696601471">Greetings all!</span></div><div id="yiv1813008296yui_3_2_0_17_131440696601448"><span id="yiv1813008296yui_3_2_0_17_131440696601471"><br></span></div><div id="yiv1813008296yui_3_2_0_17_131440696601448">This October, a six-port paper will be included in the Proceedings of Microwave Update 2011. If you read the old six-port paper, this is a major revision and expansion. </div><div id="yiv1813008296yui_3_2_0_17_131440696601448"><br></div><div id="yiv1813008296yui_3_2_0_17_131440696601448">http://www.delmarnorth.com/microwave/newsletters/sixportmodel.pdf<br id="yiv1813008296yui_3_2_0_17_131440696601495"></div><div id="yiv1813008296yui_3_2_0_17_131440696601448"><br></div><div id="yiv1813008296yui_3_2_0_17_131440696601448">Next step: building six-ports with the recently received couplers and dividers, at 1.2GHz in order to experiment with local amateur DTV. </div><div id="yiv1813008296yui_3_2_0_17_131440696601448"><br></div><div id="yiv1813008296yui_3_2_0_17_131440696601448">https://plus.google.com/114254220048556407553/posts/MVTkLTbNuXB<br id="yiv1813008296yui_3_2_0_17_1314406966014112"></div><div id="yiv1813008296yui_3_2_0_17_131440696601448"><br></div><div id="yiv1813008296yui_3_2_0_17_131440696601448">I'm hoping that experiments at 1.2GHz will produce enough know-how to make a reliable recipe, and then that recipe can be used at 3 and 5 GHz.<br id="yiv1813008296yui_3_2_0_17_1314406966014123"></div><div id="yiv1813008296yui_3_2_0_17_131440696601448"><br></div><div id="yiv1813008296yui_3_2_0_17_131440696601448">I'll be out of town until September 7th. My three children will be back in school on Monday, and I'll begin to have a lot more time to help out on MEP and related experiments. Summer is a bit more challenging in terms of having uninterrupted time.</div><div id="yiv1813008296yui_3_2_0_17_131440696601448"><br></div><div id="yiv1813008296yui_3_2_0_17_131440696601448">This list is intended to support and encourage amateur microwave engineering projects, so please speak up with ideas, comments, critiques, proposals and plans. </div><div id="yiv1813008296yui_3_2_0_17_131440696601454"><br></div><div id="yiv1813008296yui_3_2_0_17_131440696601454">Looking forward to the fall, </div><div id="yiv1813008296yui_3_2_0_17_1314406966014136">-Michelle W5NYV<br id="yiv1813008296yui_3_2_0_17_131440696601459"></div><br><div id="yiv1813008296yui_3_2_0_17_1314406966014146">Sit vis vobiscum!</div></div></div><div><meta http-equiv="x-dns-prefetch-control" content="on"></div></div>Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-67359148892272533612011-08-08T10:19:00.000-07:002011-08-08T10:20:13.491-07:00Qt4 built, building a GUI for SDRs<div style="color:#000; background-color:#fff; font-family:times new roman, new york, times, serif;font-size:12pt"><div><span>After reinstalling Xcode, Qt4 installed from the repository. This is the recommended way to build GUIs for MEP. Thanks to Jacob for highlighting Qt4 and recommending a book.</span></div><div><span><br></span></div><div><span>If you're interested in building the GUI, then install Qt and speak up! :+)</span></div><div><span><br></span></div><div><span>Tom Rondeau had some very nice things to say about a model-view-controller architecture-for-SDR letter I wrote him and fred harris a couple months back. The response got me thinking about exactly how one would want to partition tasks for an SDR, and how those partitions could improve the user experience and user interface.</span></div><div><span><br></span></div><div><span>Model-view-controller type software writing can be very user (and user-interface) focused. What I'd like to look at is how to best write a GUI for SDR. While the application is MEP, I'm looking for generalizations that will be useful to others.</span></div><div><br></div><div>What do you all think?</div><div><br></div><div>-Michelle W5NYV</div></div>Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-88104635851120470962011-07-22T15:51:00.001-07:002011-07-22T15:51:55.474-07:00Numbering Scheme, looking for hybrid couplers and dividers, and MUD?<div style="color:#000; background-color:#fff; font-family:times new roman, new york, times, serif;font-size:12pt"><div><span>Hi everyone! </span></div><div><br></div><div><span></span>Here's a document about the numbering scheme in the IQ Gain and Phase Correction Filter. </div><div><br></div><div>I bought the first set of parts for experimenting with six-port structures. Two 90 degree hybrid couplers off eBay. The target application is DVB amateur television. There's a repeater near me for DVB ATV. The frequency of interest for this experiment is 1.2GHz.</div><div><br></div><div>If you have any 90 degree hybrid couplers or power dividers for this frequency, and are willing to donate them to the cause, let me know! I'm looking for at least 4 more couplers and 2 dividers (0 degree phase, equal power dividers). </div><div><br></div><div>Does anyone have any plans to attend Microwave Update in Connecticut this year? </div><div> </div><div>-Michelle W5NYV<br></div><br></div>Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-29850216835779202872011-06-02T12:48:00.001-07:002011-06-02T12:48:49.247-07:00FPGAs in spaceArticle from EE Times about FPGAs in a cubesat project.<p><br><a href="http://www.eetimes.com/design/military-aerospace-design/4216480/High-performance-FPGAs-take-flight-in-microsatellites?cid=NL_ProgrammableLogic&Ecosystem=programmable-logic">http://www.eetimes.com/design/military-aerospace-design/4216480/High-performance-FPGAs-take-flight-in-microsatellites?cid=NL_ProgrammableLogic&Ecosystem=programmable-logic</a><p> -Michelle W5NYV <p><br>Potestatem obscuri lateris nescis.Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-45627975617717220452011-05-28T12:26:00.001-07:002011-05-28T12:26:56.845-07:00VHDL implementation compared to MATLAB model - overall successOverview of successful results with synthesizeable VHDL implementation. <br>Comparison with MATLAB results. <br> -Michelle W5NYVMichellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-34283219083457213002011-05-19T16:06:00.001-07:002011-05-19T16:06:07.604-07:00"What's Up With ARM"Here's an opinion piece about the current state of Linux development on ARM. I <br>thought it was interesting, largely agree with the author, and wanted to share <br>it with you guys.<p><a href="http://www.linux.com/news/featured-blogs/171-jonathan-corbet/445344-whats-up-with-arm">http://www.linux.com/news/featured-blogs/171-jonathan-corbet/445344-whats-up-with-arm</a><p><br>Having got the beagleboard lab back up and running after the extended tour of <br>duty doing VHDL, I find that it is very true that getting Linux working on ARM <br>can be much more "some assembly required" than, say, a desktop. It's well worth <br>it, considering how powerful the ARM family is. <p><br>In order to develop something useful for MEP on ARM, there is quite a bit of <br>slogging to do through various rough edges. When experimenting with cameras and <br>video output, nothing ever really "quite worked", and the variety and <br>duplication mentioned in the article were in full evidence.<p>The current Angstrom build I'm working with was obtained from the Narcissus <br>Angstrom image builder. I used this because I simply could not get the demo <br>build of Angstrom to cleanly update from the package server. This sort of <br>obstacle can be really frustrating. <p><br>Here is the link to generate a build of Angstrom:<br><a href="http://narcissus.angstrom-distribution.org/">http://narcissus.angstrom-distribution.org/</a><p>This image boots, but I haven't gotten much farther than launching Firefox. <p><br>More soon!<br>-Michelle W5NYVMichellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-57685638712124540062011-05-09T21:22:00.001-07:002011-05-09T21:22:09.277-07:00updated synthesizeable VHDL block - progressHere is updated VHDL code for the IQ Gain and Phase Correction filter.<p>I'm working with an adjusted numbering scheme in signed arithmetic to correct an <br>overflow problem (thanks to KB5MU, who helped identify). <p>This implementation, which is designed to be synthesizeable, is beginning to <br>function as intended. There is a factor of two error, but the compiled block <br>outputs I and Q. <p><br>With some data visualization, these might prove to be a passed-through I and <br>phase corrected Q at the output, with a massive gain overcorrection. I'll check <br>that tomorrow! <p> -Michelle W5NYVMichellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-70451377413293734322011-04-22T09:16:00.001-07:002011-04-22T09:16:55.630-07:00VHDL update - IQ Gain and Phase correction, next blocksHi everyone! I'm back to work on the VHDL after an interruption for a DXpedition <br>to Curaçao, spring break shennanigans, and photographing a wedding. <p>I took the entity, architecture, and the testbench from the variable <br>(non-synthesizeable) version, and started a new workspace. The goal is to get <br>the register-based version working. When last I attempted this, I got incorrect <br>results from multiplication. I'm making another run at it to get this filter <br>ready for synthesis (when it's put into an FPGA, instead of just working as a <br>mathematical model).<p>If you're interested in working on VHDL for MEP, there is PLENTY of opportunity. <br>It doesn't even have to be VHDL. If you work in Verilog, and can synthesize the <br>block, then go for it. <p>I'm approaching this like a slow-growing bacteria that spreads to adjacent <br>blocks in the petri dish. The next block upstream is automatic gain control. <br>I've read the wikipedia article about AGC, but that's about as far as I've <br>gotten.<p>Article here:<br><a href="http://en.wikipedia.org/wiki/Automatic_gain_control">http://en.wikipedia.org/wiki/Automatic_gain_control</a><p>Does anyone on the list have any experience with AGC design or analysis? I <br>understand why AGC is important, and I think I understand the trade-offs. I'm <br>not sure quite yet how to design a block that achieves AGC. Right now, the AGC <br>is modeled in the IQ correction block by simply dividing the incoming values of <br>the signals by the maximum expected value. <p>I'd like to replace that modeling with a block that does the AGC before the <br>samples are delivered to the filter. <p>The next block downstream is, I believe, the demodulator.<p>I have attached a pdf with the current snapshot of the IQ Gain and Phase code.<br> <br>More soon,-Michelle W5NYV<p><br>Potestatem obscuri lateris nescis.Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-83282511437423393962011-03-05T13:52:00.001-08:002011-03-05T13:52:24.791-08:00IQ Correction VHDL updateGreetings everyone,<p>I have a VHDL implementation of the IQ phase and gain correction algorithm <br>working. This implementation isn't synthesizeable in logic (yet), but it will be <br>as soon as I figure out why signed multiplication gives the wrong result.<p>Since I have a version that is working (with some of the internal math done with <br>variables instead of registers) I'm taking the opportunity to work on gain and <br>phase lock and the creation of "corrected" I and Q signals.<p>I is passed along with a filter delay, and corrected Q is passed along. <p>This part needs to be done regardless of how the internals of the correction <br>block are implemented.<p>If you haven't visited the <a href="http://opencores.com">opencores.com</a> site, then you might want to drop by <br>and check it out. We're in there! <p><br>IQ Phase and Gain Correction is the name of the project and our page is <br><a href="http://opencores.com/project,iqcorrection">http://opencores.com/project,iqcorrection</a><p>I'll have today's cut of code up there after a celebratory lunch. <br> <br>More soon (phase and gain lock signals in progress)<br>-Michelle W5NYV <p><br>Potestatem obscuri lateris nescis.Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-16807401046322365002011-02-22T21:29:00.005-08:002011-02-22T21:29:24.330-08:00Package that makes normally distributed random numbers from uniform numbersIn order to be able to have normal distribution noise, I made a package that <br>takes the uniform distribution random numbers and uses the central limit theorem <br>to give an (approximately) normal distribution. Here's the package: <p><p>library ieee;<br>use ieee.std_logic_1164.all;<br>use ieee.math_real.all;<br>use ieee.numeric_std.all;<br>use work.random_int.all;<p>--by MEP 22 February 2011<br>--usage:<br>--this is a function, which means it can be on the right-hand side<br>--of an assignment. It returns a mean-zero random number from a<br>--normal distribution. The argument is a real number that indicates<br>--the standard deviation desired. <br>--<br>--random_noise(sigma);<br>--<p>package normal_distribution_random_noise is<p> function random_noise ( <br> sigma : real)<br> return real;<p>end package normal_distribution_random_noise;<p><br>package body normal_distribution_random_noise is<p> function random_noise ( <br> sigma : real<br> )<br> return real is<br> <br> --variables<br> variable u_noise: real; --uniform distribution noise<br> variable n_noise: real := 0.0; --normal distribution noise<br> variable seed1 : positive;<br> variable seed2 : positive; <br> <br> begin<p> --obtain a uniformly distributed random number<br> uniform(seed1, seed2, u_noise);<br> --report "Random uniform noise is " & real'image(u_noise) & ".";<br> <br> for normal_count in 0 to 12 loop<br> --Turn the uniform distributed number <br> --into a normally distributed number<br> --by using the central limit theorem.<br> --Make it mean zero and make it have<br> --the range of the uniform numbers<br> --that it is composed from. <br> n_noise := n_noise + u_noise;<br> end loop;<br> <br> n_noise := n_noise - (0.5)*(real(12)); --normal distribution with a mean <br>of zero<br> --report "Random normal noise is " & real'image(n_noise) & ".";<br> n_noise := n_noise/(real(12));<br> --report "Random normal noise using range of uniform is " & <br>real'image(n_noise) & ".";<br> n_noise := sigma*n_noise;<br> <br> return n_noise;<br> end function random_noise;<br>end package body normal_distribution_random_noise;Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-72445938669774007402011-02-22T21:29:00.003-08:002011-02-22T21:29:14.435-08:00Package that creates I and Q samples to test the IQ Correction blocklibrary ieee;<br>use ieee.std_logic_1164.all;<br>use ieee.math_real.all;<br>use ieee.numeric_std.all;<br>use work.normal_distribution_random_noise.all;<p>--by MEP 22 February 2011<br>--usage:<br>--these are functions, which means they can be on the right-hand side<br>--of an assignment. These functions create an I and Q sample.<br>--The arguments are <br>--a natural number standing for the index of the sample,<br>--a real number that provides a way to have many samples per period,<br>--a real number standing for the standard deviation of the normally distributed <br>noise added to the sample,<br>--a real number standing for the amplitude of the signal,<br>--a natural number indicating the width of the vector holding the returned <br>value,<br>--a real number indicating the gain error of Q with respect to I,<br>--and a real number indicating the phase error of Q with respect to I<br>--<br>--create_I_sample(n_dat, freq, sgma, amplitude, return_width);<br>--create_Q_sample(n_dat, freq, sgma, amplitude, return_width, e1, a1);<br>--<p>package create_sample is<br> <br> function create_I_sample(<br> n_dat : integer; <br> freq : real;<br> sgma : real;<br> amplitude : real;<br> return_width : natural) <br> return signed;<br> <br> function create_Q_sample(<br> n_dat : integer; <br> freq : real;<br> sgma : real;<br> amplitude : real;<br> return_width : natural; --x1_tb'LENGTH<br> e1 : real; --gain error<br> a1 : real) --phase error <br> return signed;<br> <br>end package create_sample;<p><br>package body create_sample is<br> <br> function create_I_sample(<br> n_dat : integer; <br> freq : real;<br> sgma : real;<br> amplitude : real;<br> return_width : natural) --x1_tb'LENGTH<br> return signed is<p> variable local_x1 : real;<br> variable int_x1: integer;<br> variable returned_x1 : signed(return_width downto 0);<br> <br> begin<p> local_x1 := amplitude*sin(2.0*math_pi*(real(n_dat))*freq) + <br>random_noise(sgma);<br> --report "local_x1 inside CREATE_I_SAMPLE function is " & <br>real'image(local_x1) & ".";<br> <br> --AGC scaling. Scaling factor is maximum value the signal can take. <br> local_x1 := local_x1/(1.11); <br> --report "local_x1 after AGC inside CREATE_I_SAMPLE function is " & <br>real'image(local_x1) & ".";<br> <br> int_x1 := integer(trunc(local_x1*((2.0**31.0)-1.0))); --scaled<br> --report "integer version of x1 inside CREATE_I_SAMPLE function is " & <br>integer'image(int_x1) & ".";<br> <br> returned_x1 := (to_signed(int_x1, return_width+1));<br> <br> return returned_x1;<br>end function; <p>function create_Q_sample(<br> n_dat : integer; <br> freq : real;<br> sgma : real;<br> amplitude : real;<br> return_width : natural; --x1_tb'LENGTH<br> e1 : real; --gain error<br> a1 : real) <br> return signed is<p> variable local_y1 : real;<br> variable int_y1: integer;<br> variable returned_y1 : signed(return_width downto 0);<br> <br> begin<br> local_y1 := amplitude*(1.0 + e1)*cos(2.0*math_pi*(real(n_dat))*freq + <br>a1) + random_noise(sgma);<br> --report "local_y1 first created CREATE_Q_SAMPLE function is " & <br>real'image(local_y1) & ".";<br> <br> --AGC scaling. Scaling factor is maximum value the signal can take.<br> local_y1 := local_y1/(1.11); <br> --report "local_y1 after AGC inside CREATE_Q_SAMPLE function is " & <br>real'image(local_y1) & ".";<br> <br> int_y1 := integer(trunc(local_y1*((2.0**31.0)-1.0))); --scaled<br> --report "integer version of y1 inside CREATE_Q_SAMPLE function is " & <br>integer'image(int_y1) & ".";<br> <br> returned_y1 := (to_signed(int_y1, return_width+1));<br> <br> return returned_y1;<br> end function;<br>end package body create_sample;Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-3478005502542191022011-02-22T21:29:00.001-08:002011-02-22T21:29:06.517-08:00IQ Phase Gain Correction testbenchlibrary ieee;<br>use ieee.std_logic_1164.all;<br>use ieee.math_real.all;<br>use ieee.numeric_std.all;<br>use work.normal_distribution_random_noise.all;<br>use work.create_sample.all;<p>entity IQGainPhaseCorrection_testbench is<br>end entity;<p><br>architecture IQGainPhaseCorrection_testbench_arch of <br>IQGainPhaseCorrection_testbench is<p>--declare the DUT as a component.<br>component IQGainPhaseCorrection is<br> generic(width :natural);<br> port(<br> clk :in std_logic;<br> x1 :in signed(width downto 0);<br> y1 :in signed(width downto 0);<br> gain_error :out signed(width downto 0);<br> gain_lock :out bit;<br> phase_error :out signed(width downto 0);<br> phase_lock :out bit;<br> corrected_x1 :out signed(width downto 0);<br> corrected_y1 :out signed(width downto 0)<br> );<br> end component;<p>--provide signals to run the DUT.<br>signal clk_tb : std_logic := '0';<br>signal clk_tb_delayed : std_logic := '0';<br>signal x1_tb : signed(31 downto 0);<br>signal y1_tb : signed(31 downto 0);<br>signal gain_error_tb : signed(31 downto 0);<br>signal gain_lock_tb : bit;<br>signal phase_error_tb : signed(31 downto 0);<br>signal phase_lock_tb : bit;<br>signal corrected_x1_tb : signed(31 downto 0);<br>signal corrected_y1_tb : signed(31 downto 0);<p>begin<p> --connect the testbench signal to the component<br> DUT:IQGainPhaseCorrection<br> generic map(<br> width => 31<br> )<br> port map(<br> clk => clk_tb_delayed,<br> x1 => x1_tb,<br> y1 => y1_tb,<br> gain_error => gain_error_tb,<br> gain_lock => gain_lock_tb,<br> phase_error => phase_error_tb,<br> phase_lock => phase_lock_tb,<br> corrected_x1 => corrected_x1_tb,<br> corrected_y1 => corrected_y1_tb<br> );<p> <br>--create I and Q. MTreseler says, "sin in vhdl I use use ieee.math_real.all and <br>cast to integer."<p>CREATE_I_Q_SAMPLES: process (clk_tb) is<br>--for both I and Q<br>variable n_dat : integer := 0;<br>variable freq : real := 0.03; --relative frequency<br>variable sgma : real :=0.01; --sigma of noise<br>variable amplitude : real := 1.0; --amplitude<br>--for Q<br>variable e1 : real := 0.1; --gain error<br>variable a1 : real := (10.0*math_pi)/180.0; --phase error of 10 degrees<p>begin<br> if (clk_tb'event and clk_tb = '1') then<br> x1_tb <= create_I_sample(n_dat, freq, sgma, amplitude, 31);<br> y1_tb <= create_Q_sample(n_dat, freq, sgma, amplitude, 31, e1, a1);<br> n_dat := n_dat + 1;<br> end if;<br>end process CREATE_I_Q_SAMPLES;<p><br>DRIVE_CLOCK:process<br>begin <br> wait for 50 ns;<br> clk_tb <= not clk_tb;<br> clk_tb_delayed <= not clk_tb_delayed after 1 ns;<br>end process;<p>end IQGainPhaseCorrection_testbench_arch;Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-17920758104114838552011-02-22T21:28:00.003-08:002011-02-22T21:28:56.241-08:00IQ Phase Gain Correction architecturearchitecture IQGainPhaseCorrection_beh of IQGainPhaseCorrection is<p> --signal declarations<p> --phase error estimate accumulator<br> signal reg_1:signed(width downto 0) := (others => '0');<p> --gain error estimate accumulator<br> signal reg_2:signed(width downto 0) := (0 => '1', others => '0');<br> <br> --Phase Offset Adjustment Applied to y1<br> signal y2:signed(width downto 0) := (others => '0');<p> --Gain and Phase Adjustment Applied to y1<br> signal y3:signed(2*width+1 downto 0) := (others => '0'); <br> <br> signal x1y2:signed(2*width+1 downto 0):= (others => '0');<br> signal mu_1:signed(width downto 0):= (others => '0');<br> signal x1x1y3y3:signed(width downto 0):= (others => '0');<br> signal mu_2:signed(width downto 0):= (others => '0');<br> <br> signal reg_1x1:signed(2*width+1 downto 0):= (others => '0');<br> signal y3y3: signed(4*width+3 downto 0):= (others => '0');<br> signal x1x1: signed(2*width+1 downto 0):= (others => '0');<br> <br>begin<p> correction : process (clk) is <br> begin<br> <br> if clk'event and clk = '1' then<br> <br> --phase error estimate, step size set to 0.000244<br> --which is achieved with a shift right by 12.<br> reg_1x1 <= reg_1 * x1; --clock 0<br> y2 <= y1 - reg_1x1(2*width+1 downto width+1); --clock 1<br> x1y2 <= x1 * y2; --clock 2<br> mu_1 <= shift_right(x1y2(2*width+1 downto width+1),12); --step size <br>applied. --clock 3<br> reg_1 <= reg_1 + mu_1; --clock 4<br> phase_error <= reg_1; --update phase error estimate. --clock 5<br> <br> --gain error estimate, step size set to 0.000122<br> --which is achieved with a shift right by 13.<br> y3 <= y2 * reg_2; --clock 0 --63 downto 0 n*32 - 1, n = 2<br> x1x1 <= x1 * x1; --clock 0 --63 downto 0<br> y3y3 <= y3 * y3; --clock 1 --127 downto 0 n*32 -1, n = 4 to <br>n = 3<br> x1x1y3y3 <= (abs(x1x1(2*width+1 downto width+1))) - (abs(y3y3(4*width+3 <br>downto 3*width+3))); --clock 2<br> mu_2 <= shift_right(x1x1y3y3, 13); --clock 3<br> reg_2 <= reg_2 + mu_2; --clock 4<br> gain_error <= reg_2; --update gain error estimate. --clock 5<br> <br> end if;<br> <br> end process; <p>end IQGainPhaseCorrection_beh;Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-39593547932969403062011-02-22T21:28:00.001-08:002011-02-22T21:28:47.010-08:00IQ Phase Gain Correction entitylibrary ieee;<br>use ieee.std_logic_1164.all;<br>use ieee.std_logic_arith;<br>use ieee.numeric_std.all; <p><br>entity IQGainPhaseCorrection is<p>generic(width:natural);<p>port(<br> clk :in std_logic;<br> x1 :in signed(width downto 0);<br> y1 :in signed(width downto 0);<br> gain_error :out signed(width downto 0);<br> gain_lock :out bit;<br> phase_error :out signed(width downto 0);<br> phase_lock :out bit;<br> corrected_x1 :out signed(width downto 0);<br> corrected_y1 :out signed(width downto 0)<br> );<p>end IQGainPhaseCorrection;Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-11477748837416217372011-02-22T11:14:00.001-08:002011-02-22T11:14:15.846-08:00IQ Phase and Gain Correction - TestbenchBelow is the testbench for the IQ Phase and Gain Correction. <p>As you can see, there's a lot more going on in the testbench than in the block <br>for the algorithm. This is because the testbench has to generate the test <br>signals and provide the clock and establish the various settings for the test, <br>and that all adds up in this case to more lines of code. <p><br>On the list of improvements is to move the I and Q signal creation into a <br>procedure. This encapsulates code and will make the testbench a lot more <br>readable. <p><br>Another obvious improvement is to figure out exactly why the gain correction <br>isn't working yet. <p><br>More soon,<br>-Michelle W5NYV<p><br>library ieee;<br>use ieee.std_logic_1164.all;<br>use ieee.math_real.all;<br>use ieee.numeric_std.all; <p>entity IQGainPhaseCorrection_testbench is<br>end entity;<p>architecture IQGainPhaseCorrection_testbench_arch of <br>IQGainPhaseCorrection_testbench is<br>--declare the DUT as a component.<br>component IQGainPhaseCorrection is<br> generic(width :natural);<br> port(<br> clk :in std_logic;<br> x1 :in signed(width downto 0);<br> y1 :in signed(width downto 0);<br> gain_error :out signed(width downto 0);<br> gain_lock :out bit;<br> phase_error :out signed(width downto 0);<br> phase_lock :out bit;<br> corrected_x1 :out signed(width downto 0);<br> corrected_y1 :out signed(width downto 0)<br> );<br> end component;<p>--provide signals to run the DUT.<br>signal clk_tb : std_logic := '0';<br>signal x1_tb : signed(31 downto 0);<br>signal y1_tb : signed(31 downto 0);<br>signal gain_error_tb : signed(31 downto 0);<br>signal gain_lock_tb : bit;<br>signal phase_error_tb : signed(31 downto 0);<br>signal phase_lock_tb : bit;<br>signal corrected_x1_tb : signed(31 downto 0);<br>signal corrected_y1_tb : signed(31 downto 0);<p>begin<p> --connect the testbench signal to the component<br> DUT:IQGainPhaseCorrection<br> generic map(<br> width => 31<br> )<br> port map(<br> clk => clk_tb,<br> x1 => x1_tb,<br> y1 => y1_tb,<br> gain_error => gain_error_tb,<br> gain_lock => gain_lock_tb,<br> phase_error => phase_error_tb,<br> phase_lock => phase_lock_tb,<br> corrected_x1 => corrected_x1_tb,<br> corrected_y1 => corrected_y1_tb<br> );<p> <br>--create x1 and y1. MTreseler says, "sin in vhdl I use use ieee.math_real.all <br>and cast to integer."<p><br>CREATE_X1_I: process<br>variable angle : real;<br>variable local_x1 : real;<br>variable sgma : real :=0.01; --sigma of noise<br>variable amplitude : real := 1.0; --amplitude<br>variable freq : real := 0.03; --relative frequency<br>variable u_noise: real; --uniform distribution noise<br>variable n_noise: real := 0.0; --normal distribution noise<br> <br>variable seed1 : positive := 10;<br>variable seed2 : positive := 200;<p>--loop controls<br>variable make_normal_count : integer := 12;<br>variable n_dat : integer := 4;<p>variable int_x1: integer;<p>begin<br> for n_dat_count in 0 to n_dat loop<br> --make a random number<br> uniform(seed1, seed2, u_noise);<br> report "Random uniform noise in I creation is " & real'image(u_noise) & <br>".";<br> <br> for normal_count in 0 to make_normal_count loop<br> --turn the uniform distributed number <br> --into a normally distributed number<br> --by using the central limit theorem.<br> n_noise := n_noise + u_noise;<br> end loop;<br> n_noise := n_noise - (0.5)*(real(make_normal_count)); --normal <br>distribution with a mean of zero<br> report "Random normal noise in I creation is " & real'image(n_noise) & <br>".";<br> n_noise := n_noise/(real(make_normal_count)); --max values reduced?<br> report "Random normal noise (normalized?) in I creation is " & <br>real'image(n_noise) & ".";<br> <br> local_x1 := amplitude*cos(2.0*math_pi*(real(n_dat_count))*freq) + <br>sgma*(n_noise);<br> --local_x1 := cos(2.0*math_pi*(real(n_dat_count))*freq); --simpler <br>version<br> <br> --AGC scaling<br> local_x1 := local_x1/(1.01); <br> <br> report "local_x1 is " & real'image(local_x1) & ".";<br> --x1_tb <= local_x1; --somehow get real turned into signed.<br> -- 1. rescale to 0..(nearly)4096, find integer part<br> --int_x1 := INTEGER(TRUNC(local_x1*4294967296.0)); -- from random_vector<br> <br> <br> int_x1 := integer(trunc(local_x1*(2.0**31.0))); --scaled<br> <br> report "integer version of x1 is " & integer'image(int_x1) & ".";<br> -- 2. convert to signed<br> x1_tb <= (to_signed(int_x1, x1_tb'LENGTH));<p> <br> end loop;<br> wait;<br> <br>end process CREATE_X1_I;<p><br>CREATE_Y1_Q: process<br>variable angle : real;<br>variable local_y1 : real;<br>variable e1 : real := 0.1; --gain error<br>variable a1 : real := (10.0*math_pi)/180.0; --phase error of 10 degrees<br>variable sgma : real := 0.01; --sigma of noise<br>variable amplitude : real := 1.0; --amplitude<br>variable freq : real := 0.03; --relative frequency<br>variable u_noise: real; --uniformly distributed noise<br>variable n_noise: real := 0.0; --normally distributed noise<br>variable seed1 : positive := 1;<br>variable seed2 : positive := 2;<p>--loop controls<br>variable make_normal_count : integer := 12;<br>variable n_dat : integer := 4;<p>variable int_y1: integer;<br>begin<br> <br> for n_dat_count in 0 to n_dat loop<br> --make a random number<br> uniform(seed1, seed2, u_noise);<br> report "Random uniform noise in I creation is " & real'image(u_noise) & <br>".";<br> <br> for normal_count in 0 to make_normal_count loop<br> --turn the uniform distributed number <br> --into a normally distributed number<br> --by using the central limit theorem.<br> n_noise := n_noise + u_noise;<br> end loop;<br> n_noise := n_noise - (0.5)*(real(make_normal_count));<br> n_noise := n_noise/(real(make_normal_count)); --reduce size of noise<br> report "Random normal noise in I creation is " & real'image(n_noise) & <br>".";<br> n_noise := n_noise/(real(make_normal_count)); --max values reduced?<br> report "Random normal noise (normalized?) in I creation is " & <br>real'image(n_noise) & ".";<br> <br> local_y1 := amplitude*(1.0 + e1)*cos(2.0*math_pi*(real(n_dat_count))*freq + <br>a1) + sgma*(n_noise);<br> <br> --AGC scaling<br> local_y1 := local_y1/(1.01);<br> <br> --int_y1 := INTEGER(TRUNC(local_y1*4294967296.0)); -- from random_vector <br> int_y1 := integer(trunc(local_y1*(2.0**31.0))); --scaled<br> report "integer version of y1 is " & integer'image(int_y1) & ".";<br> <br> -- 2. convert to signed<br> y1_tb <= (to_signed(int_y1, y1_tb'LENGTH));<p> end loop;<br> wait;<br> <br>end process CREATE_Y1_Q;<p><br>DRIVE_CLOCK:process<br>begin <br> clk_tb <= not clk_tb;<br> wait for 50 ns;<br>end process;<p><p><p><p>end IQGainPhaseCorrection_testbench_arch;Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-35866753721882793412011-02-22T11:01:00.001-08:002011-02-22T11:01:36.432-08:00IQ Phase and Gain CorrectionI'm working on the IQ Phase and Gain Correction VHDL implementation today. Here <br>is the entity and architecture below.<p>In the testbench, the phase correction works (with some amount of oscillation), <br>but the gain correction increases without bound. Trying to track that down <br>today. I'll post the testbench next in a separate email.<p><p>library ieee;<br>use ieee.std_logic_1164.all;<br>use ieee.std_logic_arith;<br>use ieee.numeric_std.all; <p>entity IQGainPhaseCorrection is<p>generic(width:natural);<p>port(<br> clk :in std_logic;<br> x1 :in signed(width downto 0);<br> y1 :in signed(width downto 0);<br> gain_error :out signed(width downto 0);<br> gain_lock :out bit;<br> phase_error :out signed(width downto 0);<br> phase_lock :out bit;<br> corrected_x1 :out signed(width downto 0);<br> corrected_y1 :out signed(width downto 0)<br> );<p>end IQGainPhaseCorrection;<p><br>architecture IQGainPhaseCorrection_beh of IQGainPhaseCorrection is<p> --signal declarations<p> --phase error estimate accumulator<br> signal reg_1:signed(width downto 0) := (others => '0');<p> --gain error estimate accumulator<br> signal reg_2:signed(width downto 0) := (0 => '1', others => '0');<br> <br> --Phase Offset Adjustment Applied to y1<br> signal y2:signed(width downto 0) := (others => '0');<p> --Gain and Phase Adjustment Applied to y1<br> signal y3:signed(2*width+1 downto 0) := (others => '0'); <br> <br> signal x1y2:signed(2*width+1 downto 0):= (others => '0');<br> signal mu_1:signed(width downto 0):= (others => '0');<br> signal x1x1y3y3:signed(width downto 0):= (others => '0');<br> signal mu_2:signed(width downto 0):= (others => '0');<br> <br> signal reg_1x1:signed(2*width+1 downto 0):= (others => '0');<br> signal y3y3: signed(4*width+3 downto 0):= (others => '0');<br> signal x1x1: signed(2*width+1 downto 0):= (others => '0');<br> <br>begin<p> correction : process (clk) is <br> begin<br> <br> if clk'event and clk = '1' then<br> <br> --phase error estimate, step size set to 0.000244<br> --which is achieved with a shift right by 12.<br> reg_1x1 <= reg_1 * x1; --clock 0<br> y2 <= y1 - reg_1x1(2*width+1 downto width+1); --clock 1<br> x1y2 <= x1 * y2; --clock 2<br> mu_1 <= shift_right(x1y2(2*width+1 downto width+1),12); --step size <br>applied. --clock 3<br> reg_1 <= reg_1 + mu_1; --clock 4<br> phase_error <= reg_1; --update phase error estimate. --clock 5<br> <br> --gain error estimate, step size set to 0.000122<br> --which is achieved with a shift right by 13.<br> y3 <= y2 * reg_2; --clock 0 --63 downto 0 n*32 - 1, n = 2<br> x1x1 <= x1 * x1; --clock 0 --63 downto 0<br> y3y3 <= y3 * y3; --clock 1 --127 downto 0 n*32 -1, n = 4 to <br>n = 3<br> x1x1y3y3 <= (abs(x1x1(2*width+1 downto width+1))) - (abs(y3y3(4*width+3 <br>downto 3*width+3))); --clock 2<br> mu_2 <= shift_right(x1x1y3y3, 13); --clock 3<br> reg_2 <= reg_2 + mu_2; --clock 4<br> gain_error <= reg_2; --update gain error estimate. --clock 5<br> <br> end if;<br> <br> end process; <p>end IQGainPhaseCorrection_beh;Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-70546348429809309872011-02-17T18:29:00.001-08:002011-02-17T18:29:37.145-08:00VHDL experience so farI'm halfway through the VHDL class and well into implementing the IQ Phase and <br>Gain correction algorithm. I'll publish a cut of it in a separate email.<p>What I wanted to share was a few very brief observations about learning VHDL.<p>The actual description of what you want to accomplish may take much less time <br>than constructing a test that really tests what you have designed.<p>VHDL projects are usually broken down into components, which are the blocks that <br>implement your function, and testbenches, which (as the name implies) are <br>constructed logic that proves the block that implements the function does <br>what you intended to tell it to do.<p>So far, the proportion of time spent designing the block that implements the <br>function vs. designing the testbench for it is about 4:1. I don't expect this to <br>change throughout the remaining 5 weeks of the course. <p>VHDL is very strongly typed, and most of the issues I've had so far have been <br>getting used to this. Once you get the hang of it, it does get better, and makes <br>it easy to catch most errors. <p> <br>We're using the student version of Aldec Active-HDL for the development <br>environment. I have to say I like it a bit more than the Xilinx ISE webpack, but <br>the differences are minor, and the Aldec license is good for only a year at a <br>time. <p><br>More soon!-Michelle W5NYV <p><br>Potestatem obscuri lateris nescis.Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-22556234133685099602011-02-12T18:32:00.001-08:002011-02-12T18:32:57.929-08:00Software-defined radio ideasFrom twitter this past week, Tom Rondeau asked: "I'm giving a day-long lecture <br>on SDR. What would you want to hear about? I'm focusing on software and <br>processing."<p>Tom Rondeau is giving a talk with fred harris, a well-known DSP lecturer and <br>professor at SDSU. <p><br>Balister offered, "Explain the difference between a collection of functions that <br>do operations and a framework providing structure for using them."<p>What do you all think? What are the current concerns in software-defined radio <br>design? I have some ideas, but I'm very interested in what you all think.<br> -Michelle W5NYVMichellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-59800729692632999232011-01-23T21:13:00.001-08:002011-01-23T21:19:05.559-08:00Pressing on with IQ Correction algorithm - vhdl entity and architecture updateHere's tonight's progress on the entity and architecture for the implementation <br />
of the IQ Correction algorithm.<br />
<br />
It compiled after solving some trouble I had with implmenting shifts. Standard <br />
logic vectors can't be shifted, but signed vectors can be. So converting, then <br />
shifting, then converting back did the trick. <br />
<br />
More soon,<br />
-Michelle W5NYV<br />
<br />
<br />
<br />
library ieee;<br />
use ieee.std_logic_1164.all; <br />
use IEEE.std_logic_signed.all;<br />
use ieee.numeric_std.all; <br />
<br />
entity IQGainPhaseCorrection is<br />
generic(input_width:natural:=15;<br />
output_width:natural:=31);<br />
port(<br />
clk :in std_logic;<br />
x1 :in std_logic_vector(input_width downto 0);<br />
y1 :in std_logic_vector(input_width downto 0);<br />
gain_error :out std_logic_vector(output_width downto 0);<br />
phase_error :out std_logic_vector(output_width downto 0)<br />
);<br />
end IQGainPhaseCorrection;<br />
<br />
<br />
architecture IQGainPhaseCorrection_beh of IQGainPhaseCorrection is <br />
--signal declarations <br />
--phase error calculation<br />
signal reg_1:std_logic_vector(input_width downto 0);<br />
signal reg_1_sv:std_logic_vector(input_width downto 0);<br />
--gain error calculation<br />
signal reg_2:std_logic_vector(input_width downto 0);<br />
signal reg_2_sv:std_logic_vector(input_width downto 0);<br />
<br />
--Phase Offset Corrected<br />
signal y2:std_logic_vector(2*input_width downto 0);<br />
<br />
--Gain and Phase Offset Corrected<br />
signal y3:std_logic_vector(input_width downto 0); <br />
signal x1y2:signed(2*input_width downto 0);<br />
signal mu_1:signed(2*input_width downto 0);<br />
signal x1x1y3y3:signed(4*input_width downto 0);<br />
signal mu_2:signed(2*input_width downto 0);<br />
<br />
begin<br />
correction : process <br />
begin<br />
wait until clk'event and clk = '1';<br />
<br />
--phase error estimate, step size set to 0.000244<br />
y2 <= y1 - reg_1 * x1;<br />
--reg_1_sv <= reg_1;<br />
x1y2 <= signed(x1 * y2); --have to convert to signed to use shift.<br />
mu_1 <= shift_right(x1y2,12); --step size applied.<br />
reg_1 <= reg_1 + std_logic_vector(mu_1); --convert back to std_logic_vector.<br />
phase_error <= reg_1; --update phase error estimate.<br />
<br />
--gain error estimate, step size set to 0.000122<br />
y3 <= y2 * reg_2;<br />
--reg_2_sv <= reg_2;<br />
x1x1y3y3 <= signed(abs((x1)*(x1)) - abs((y3)*(y3))); --have to convert to signed to use shift.<br />
mu_2 <= shift_right(x1x1y3y3, 13); --step size applied.<br />
reg_2 <= reg_2 + std_logic_vector(mu_2); --convert back to std_logic_vector.<br />
gain_error <= reg_2; --update gain error estimate.<br />
<br />
end process;<br />
end IQGainPhaseCorrection_beh;Michellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-68423643529582306982011-01-19T20:59:00.000-08:002011-01-19T21:00:02.006-08:00IQ Correction Model - proposed plotting change, question about absolute valuesPDF attached. <p><br>More soon! -Michelle W5NYVMichellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0tag:blogger.com,1999:blog-410288222235817148.post-51243442258627738142011-01-16T22:09:00.001-08:002011-01-16T22:09:20.638-08:00IQ Correct entity and architecture files - updateHere's the snapshot of the latest work on the entity and architecture for the IQ <br>gain and phase correction algorithm. <p><p>more soon!<br>-Michelle W5NYVMichellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com2tag:blogger.com,1999:blog-410288222235817148.post-60166843131549098142011-01-13T21:04:00.001-08:002011-01-13T21:04:40.719-08:00IQ Correction entity, architecture updateentity IQGainPhaseCorrection is<p>generic(input_width:natural:=12;<br> output_width:natural:=7);<p>port(<br> clk:in bit;<br> x1:in bit_vector(input_width downto 0);<br> y1:in bit_vector(input_width downto 0);<br> gain_error:out bit_vector(output_width downto 0);<br> phase_error:out bit_vector(output_width downto 0)<br>);<p>end IQGainPhaseCorrection;<p>architecture IQGainPhaseCorrection_beh of IQGainPhaseCorrection is<p><p><br>begin<p>--as long as there are samples, do a loop<p> correction : process is<br> <br> --local variables<br> variable count_value : natural := 0;<br> <br> --phase error calculation<br> variable reg_1:bit_vector(7 downto 0):=00000000;<br> variable reg_1_sv:bit_vector(7 downto 0):=00000000;<p> --gain error calculation<br> variable reg_2:bit_vector(7 downto 0):=00000001;<br> variable reg_2_sv:bit_vector(7 downto 0):=00000000;<p> --SNR scaling?<br> constant mu_1:real:=0.0002;<br> constant mu_2:real:=0.0001;<p> --Phase Offset Corrected<br> variable y2:bit_vector(7 downto 0):=00000000;<p> --Gain and Phase Offset Corrected<br> variable y3:bit_vector(7 downto 0):=00000000;<p> begin<p> loop<br> wait until clk;<br> <br> y2(nn) = y1(nn)-reg_1*x1(nn);<br> reg_1_sv(nn) = reg_1;<br> reg_1 = reg_1 + mu_1*x1(nn)*y2(nn);
<br> <br> y3(nn) = y2(nn)*reg_2;<br> reg_2_sv(nn) = reg_2;<br> reg_2 = reg_2+mu_2*(abs(x1(nn))^2 - abs(y3(nn))^2);<p> end loop;<br> end process correction;<p>end IQGainPhaseCorrection_beh;<p><br>Attached are the entity and architecture for the IQ Correction algorithm, as <br>well as the original MATLAB model.<p>I added a clock to the entity, and started the architecture. The architecture is <br>"sketch" stage, but you can see where I'm going with it. <br> <br>Got some advice from Ken Easton on how to handle the types, and we're set to <br>talk again about how best to handle memory. <p>more soon! -Michelle W5NYVMichellehttp://www.blogger.com/profile/12516156190562527937noreply@blogger.com0