I started reading a book about reconfigurable computing.
This type of computing uses FPGAs in order to perform computations. The CPU chooses from a variety of configurations in order to set up an FPGA to solve a particular problem or set of problems. One has to figure out if the overhead of reconfiguring the FPGAs is worth the time saved by dedicated hardware (the designs in the FPGAs). It's made for some interesting reading, that's for sure. I got the book thinking it would be about general FPGA usage, but reconfigurable computing is somewhat of a specialized field that uses FPGAs as a tool to get the job done. "Real" reconfigurable computers have been designed and built and used successfully, but the market just isn't there for most companies that have tried to build reconfigurable computers as a commercial endeavor.
Now, there isn't that much here that affects MEP. Our computations are not (I don't think) difficult or wide-ranging enough to have to build a configuration management processor and swap out configurations. However, the chapter on learning VHDL is useful, and the compute vs. dataflow modeling explanations were illuminating and (to me) fun to read.
The free version of the older Integrated Software Environment (version 10.1 of the ISE) for Xilinx FPGA development did not support the larger Virtex II FPGA in the XtremeDSP Development kit. I downloaded the current free version of the ISE, and as expected, it didn't support families of FPGAs earlier than the Virtex IV.
I updated it from (free) version 11.1 to (free) version 11.5, which added the very latest Spartan 6 family to the ISE. While there isn't any target hardware doing it this way, it does allow us to develop for the latest versions of the Xilinx Spartan chip. I packed up the development station that we were loaned and will deliver it back this weekend with our thanks.
To participate in MEP FPGA design, then download the 11.1 Webpack ISE from Xilinx and update it. When you update it, there will be one DSP-related thing that you will not be able to include. Uncheck that box, and you will be able to update to 11.5 for free.
Here is a page of Xilinx ISE 11 tutorials.
I decided to look around for other amateur radio FPGA projects and found some mention of FPGA in amateur radio in a TAPR newsletter and found a modem project by a ham, which was implemented using Xilinx FPGAs. Summary is below.
Ham Radio Systems On A Chip by Steve Bragg KA9MVA from TAPR Packet Status Register #102 located at http://www.tapr.org/psr/psr102.pdf
"...the latest field programmable gate arrays (FPGAs) pack enough digital hardware to be called SoCs in their own right. Falling prices, exponentially increasing gate counts, and low-cost design software are converging to make FPGAs the right technology for emerging ham radio systems-on-a-chip."
"A ham radio SoC includes signal processing 'blocks' for the most popular modes of ham radio: analog and digital voice, ATV/SSTV, packet, data and APRS®. Vocoders and decoders, such as that developed by G4GUO and G4JNT3 can be included. Audio processing (such as speech processing, VOX and stereo synthesis) can be in the SoC. Packet engines and TNCs should also be included.
An example of an FPGA-based TNC device is Nico Palermo, IV3NWV's YAM modem4, released in 1997. The TNC-like YAM was based on the Xilinx XC5200-series FPGA, the equivalent about 3,000 gates5. IV3NWV's clever coding crammed both 1200-bit/s AFSK and 9600-bit/s G3RUH modems into a small Xilinx FPGA. Today, the equivalent of the YAM, and much more besides, can be incorporated into a ham radio SoC."
The YAM (Yet Another Modem) Modem can be read about here:
Three configuration files can be downloaded by email request. The "features" section discusses the details of the modem.