IQ Correct entity and architecture files - update

Here's the snapshot of the latest work on the entity and architecture for the IQ
gain and phase correction algorithm.

more soon!
-Michelle W5NYV

IQ Correction entity, architecture update

entity IQGainPhaseCorrection is

generic(input_width:natural:=12;
output_width:natural:=7);

port(
clk:in bit;
x1:in bit_vector(input_width downto 0);
y1:in bit_vector(input_width downto 0);
gain_error:out bit_vector(output_width downto 0);
phase_error:out bit_vector(output_width downto 0)
);

end IQGainPhaseCorrection;

architecture IQGainPhaseCorrection_beh of IQGainPhaseCorrection is

begin

--as long as there are samples, do a loop

correction : process is

--local variables
variable count_value : natural := 0;

--phase error calculation
variable reg_1:bit_vector(7 downto 0):=00000000;
variable reg_1_sv:bit_vector(7 downto 0):=00000000;

--gain error calculation
variable reg_2:bit_vector(7 downto 0):=00000001;
variable reg_2_sv:bit_vector(7 downto 0):=00000000;

--SNR scaling?
constant mu_1:real:=0.0002;
constant mu_2:real:=0.0001;

--Phase Offset Corrected
variable y2:bit_vector(7 downto 0):=00000000;

--Gain and Phase Offset Corrected
variable y3:bit_vector(7 downto 0):=00000000;

begin

loop
wait until clk;

y2(nn) = y1(nn)-reg_1*x1(nn);
reg_1_sv(nn) = reg_1;
reg_1 = reg_1 + mu_1*x1(nn)*y2(nn);

y3(nn) = y2(nn)*reg_2;
reg_2_sv(nn) = reg_2;
reg_2 = reg_2+mu_2*(abs(x1(nn))^2 - abs(y3(nn))^2);

end loop;
end process correction;

end IQGainPhaseCorrection_beh;

Attached are the entity and architecture for the IQ Correction algorithm, as
well as the original MATLAB model.

I added a clock to the entity, and started the architecture. The architecture is
"sketch" stage, but you can see where I'm going with it.

Got some advice from Ken Easton on how to handle the types, and we're set to
talk again about how best to handle memory.

more soon! -Michelle W5NYV

VHDL entity for the IQ Gain and Phase Correction algorithm (Tuesday Challenge!)

entity IQGainPhaseCorrection is

generic(input_width:natural:=7;
output_width:natural:=7);

port(
x1:in bit_vector(input_width downto 0);
y1:in bit_vector(input_width downto 0);
gain_error:out bit_vector(output_width downto 0);
phase_error:out bit_vector(output_width downto 0)
);

end IQGainPhaseCorrection;

Hi Everyone,

Here's the entity:

--------------------------
entity IQGainPhaseCorrection is

generic(input_width:natural:=7;
output_width:natural:=7);

port(
x1:in bit_vector(input_width downto 0);
y1:in bit_vector(input_width downto 0);
gain_error:out bit_vector(output_width downto 0);
phase_error:out bit_vector(output_width downto 0)
);

end IQGainPhaseCorrection;
--------------------------

An entity in VHDL is the interface to the outside world. It's equivalent to the
list of pins of an IC that you might want to use in a project.

Here, there are two inputs, the I and Q signals, and two outputs, the gain error
and the phase error between the two signals, so that the errors can be
corrected.

The "generic" keyword allows parameters in VHDL to be set. You can see that
there's an input width and an output width. It allows flexibility and reuse in
VHDL.

My question: Is 8-bit widths for both reasonable?

IQ Correction Algorithm - beginning

Greeting everyone,

Attached is the IQ Correction MATLAB model written by Bob McGwier, and the
output figures it produced after I got it working in Octave.

Two signals, x1 and y1, are created in this model. They represent I and Q
signals. Both have noise added to them (random, normal distribution, mean zero,
0.01 standard deviation).

Whenever we implement a circuit that handles I and Q, we expect to get
differences between I and Q that are due to the implementation. In this model,
y1 has a fixed gain error and a fixed phase error. The IQ correction algorithm
determines the gain error and phase error. Neat!

Running the model under Octave, I got the following when the model attempted to
draw figure 3:

octave-3.2.3:3> IQCorrectGain_Phase
error: `kaiser' undefined near line 92 column 4
error: called from:
error: /Users/w5nyv/Dropbox/MEP/IQCorrectGain_Phase.m at line 92, column 3
octave-3.2.3:3>

That particular section of the model is:

figure(3)
subplot(3,1,1)
ww=kaiser(1024,12)';
ww=ww/sum(ww);
tt=n_dat-1023:n_dat;
plot(-0.5:1/1024:0.5-1/1024,fftshift(20*log10(abs(fft((x1(tt)+1i*y1(tt)).*ww)))))

% z=zeros(1,1024);
% for kk=1:1024
% z(kk)=(x1(tt(kk))+1i*y1(tt(kk)))*ww(kk);
% end
% plot(-0.5:1/1024:0.5-1/1024,fftshift(20*log10(abs(fft(z)))))
grid on
axis([-0.5 0.5 -140 10])
title('Output Spectrum with Gain and Phase Offset')

The kaiser reference is to a windowing function. It looked like I needed to
install an extra windowing package for Octave! Octave is a free and open source
version of MATLAB.

On the Mac,
sudo port install octave-windows
worked just fine on the desktop, and the model ran with the original MATLAB
kaiser window function.

However, a dependency wouldn't easily install on the laptop. I tried to build
from source, but running the port command again (port is somewhat similar to
opkg, git, svn etc) it still hung up on a particular dependency.

Through the power of Twitter, Bob recommended changing to another windowing
function (from kaiser to blackman-harris, which appears to be called just
blackman in Octave) and that seemed to do the trick. Since this particular
function is just to present the data, it's a bit less critical than having to
use an alternate function in the filter itself.

This is a good example of what is sometimes necessary when using Octave instead
of MATLAB. While Octave shadows MATLAB very closely, it's not an identical twin.

The very next step is to write a tutorial about the filter so that the math pops
right out at you.

The next step after that is to write the filter in VHDL. All are welcome to
participate, critique, troubleshoot! If you have experience (or want some) in
writing VHDL, here is a chance. :+)

More soon,
-Michelle W5NYV

Potestatem obscuri lateris nescis.

FPGA development station in the works

The Spartan 6 development board powered up OK.
A fresh install of Windows on the development machine has been completed.
The development environment (ISE Webpack 12.3) has been installed.

Next up: update the ISE to 12.4 and figure out how to share the station. 
 -Michelle W5NYV

Spartan-6 hardware purchased, ISE 12.4 released from Xilinx, and filter solution provided by Bob

I bought us a development kit in order to provide some hardware to work on (you all might recall that the loaner DSP-centric development kit didn't work out for us). 

The goal is to put it on the net so that any of us can access it and do development. The way to accomplish this is probably through a VPN and/or screen sharing setup. I'll have a computer dedicated to the station that will (hopefully) stay up and be accessible all the time!

Here's a link to the kit:

http://www.xilinx.com/products/devkits/EK-S6-SP601-G.htm

And, 12.4 ISE (we use the free webpack version) has just been released. This is the software that allows you to develop on Xilinx FPGAs. Here's the download link:

http://www.xilinx.com/support/download/index.htm

Please update your ISE and stay tuned for more FPGA updates   :+)

Also, Bob McGwier has provided a filter solution (which I'm sorry to say I haven't had a chance yet to do much with quite yet). Thank you Bob!

-Michelle W5NYV

Greetings everyone!

I have a question. I'm confused on page 176 in the Six-Port Technique book. I'm working on an Octave model of six-port modulation and demodulation. It takes four reflection states, modulates, then demodulates. I am expecting to be able to show how a six-port device works with this model.

Determining the demodulation coefficients is an important step. There's three matrices. A, B, and X. A is composed of power out for all ports and all reflection states. B is the constellation points defined. X is the demodulation coefficients. 

The book says to do a least squares solution for X that minimizes the norm of B=A*X. 

The problem I'm having is understanding what the right sizes for the matrices are. 

For QPSK, it would seem to me that B and X are both 8x1. However, the size for A isn't 8x8, which is (I think) what it would have to be in order to multiply A times X. 

In my case, the number of constellation points M (for QPSK) is 4. This means that X has to have 8 values. There are four sets of two values that determine the constellation points.

I'm implementing a six-port model, so the number of ports N is 4. The notation seems to indicate that the matrix A is 4x8, but multiplying a 4x8 times a 8x1 results in a 4x1 matrix, and not a 8x1 matrix.

Either I have the size of B wrong, or I have the size of A wrong. I'm pretty sure I have the size of X right.

I think the size of B for QPSK should be 8x1 because of how it's used on page 166. Each of the Powers (from 4 ports) is multiplied by a particular demodulation coefficient. If I have 4 "I" and 4 "Q", then that should be eight demodulation coefficients in all, for an 8x1 matrix.

So, given all that, I'm thinking that I'm not understanding the notation for the matrix A, or else not understanding what the vertical and horizontal bars mean within A, B, and X.

Please let me know where I'm botching this - I'm getting a constellation out at the end using an abridged X of four elements (in order to match the size and sort of limp in with a fake BPSK), but it's severely distorted, and I think getting the correct A would make the ideal-case model to behave correctly and result in a milestone being met.

I attached the model as a text file.  I know it's difficult to interpret other people's code, but here is the current version for reference.

I also attached the most recent demodulation result so you can see that the output isn't quite there yet - but it's close. I'm not sure why the title keeps getting cut off - there is possibly something I need to do to make gnuplot give me more margin so this doesn't happen, but I've been concentrating on getting the model corrected and have put off polishing the graphics for later.

Working on this is very exciting, and we've been able to make progress. I'm looking forward to making some hardware, and have found some practical references for combiners and couplers. I am still working on finding use of HFSS, but did track down someone with an older copy of the program who is supposed to bring it to me at one of the next microwave meetings, and I think Roger AD5T had a lead on a copy too. 

Using a local company's version didn't work out due to the license agreement that the company had with the vendor of HFSS.

More soon,

-Michelle W5NYV