D flip flop tested, seems to work, next steps

I wrote another two VHDL modules in the effort to test the D flip flop code. I wrote an inverter in order to have an external inverter component and get some practice with incorporating components into architectures. I also wrote an architecture module. An architecture is a collection of components linked by signals. The architecture code is at the bottom of this email. Essentially, an architecture is a circuit. The components can be thought of as devices or ICs.

So, it seems to work. The flip flop is hooked up in a way that the inverted output is fed back in to its own input. This creates a divide by two counter, and that is indeed what happens in the simulator.

What are the flip flops for? They are the building blocks of the bit error rate tester, which will be implemented in an FPGA and will be used to measure the performance of the receiver.

While this isn't bad for a beginner, and while the layout of a bit error rate tester is straightforward, the strategy for the actual receiver is not as clear-cut. I have a growing competence with what a Costas Loop does, and it's starting to make some sense, but the identification of individual modules is going to probably proceed pretty much like this effort, with the individual components being built up from very simple starting points.

Next steps:
1) Work on the website to better archive/present/share/explain the VHDL
2) Put the flip flops together to make a pseudorandom number generator and test it.

Here's the code:
----------------------------------------------------------------------------------
-- Company: Optimized Tomfoolery 
-- Engineer: Michelle Thompson
--
-- Create Date:    10:53:22 05/28/2010
-- Design Name: BERT
-- Module Name:    test_flip_flop - Behavioral
-- Project Name: MEP
-- Target Devices:
-- Tool versions:
-- Description: hook up flip flop and clock and see if it works
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_flip_flop is
 --declare signals here
 signal Tic_Toc : STD_LOGIC := '0';
 signal Output_Data : BIT := '0';
 signal Output_Data_Inverted : BIT := '0';
 signal Set : STD_LOGIC := '0';
 signal Reset : STD_LOGIC := '0';
end test_flip_flop;

architecture Behavioral of test_flip_flop is
 component clock
  generic (PULSE_WIDTH : TIME);
  port (clock: out STD_LOGIC);
 end component;
 
 component d_flip_flop
  port (data_in: in BIT;
    clock: in STD_LOGIC;
    data_out: out BIT;
    set: in STD_LOGIC;
    reset: in STD_LOGIC);
 end component;
 
 component inverter
  port (inverter_data_in: in BIT;
    inverter_data_out: out BIT);
 end component;
 

begin
 Synch: clock
  generic map (PULSE_WIDTH => 50 ns)
  port map (Tic_Toc);
  
 Invert: inverter
  port map (Output_Data, Output_Data_Inverted);
 
 Drive_Flip_Flop: d_flip_flop
  port map (Output_Data_Inverted, Tic_Toc, Output_Data, Set, Reset);
end Behavioral;
----------------------------------------------------------------------------------