Wednesday, May 26, 2010

d flip flop synthesized

After some reading and some learning, I was able to synthesize a D flip flop in VHDL using Xilinx ISE (webpack version 11).

It's a small step, but it's a building block for a pseudorandom number generator that will be used in the bit error rate tester. This tester (BERT for short) will be used as a tool to test the MEP receiver.

It's such a short bit of code so far that I'm going to include it in this email in its entirety!   :+)    
Here it is:

-- Company: Optimized Tomfoolery
-- Engineer: Michelle Thompson
-- Create Date:    08:32:51 05/26/2010
-- Design Name: Bit Error Rate Tester
-- Module Name:    d_flip_flop - Behavioral
-- Project Name: MEP
-- Target Devices:
-- Tool versions:
-- Description: A bit error rate tester for MEP receiver
-- Dependencies:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
library IEEE;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity d_flip_flop is
    Port ( data_in : in  STD_LOGIC;
           clock : in  STD_LOGIC;
           data_out : out  STD_LOGIC;
           set : in  STD_LOGIC;
           reset : in  STD_LOGIC);
end d_flip_flop;

architecture Behavioral of d_flip_flop is
 process (data_in, clock, set, reset)
 -- asynchronous reset output to 0
 if (reset = '1')
 then data_out <= '0';
  -- asynchronous set output to 1
  elsif (set = '1')
  then data_out <= '1';
  --clock rising edge
   elsif(clock='1' and clock'event)
   then data_out <= data_in;
 end if;
 end process;
end Behavioral;

Next step is to document in a way that makes it easier to participate. Then, add code that makes the inputs wiggle so that the outputs wiggle. Then, test to make sure it behaves exactly as a D flip flop should. This will be the first component in the MEP VHDL library of parts that will make up the tools and pieces of the system.

More soon!
-Michelle W5NYV

Potestatem obscuri lateris nescis.

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