and now... a clock!

In order to drive the flip flop, a clock was coded up in VHDL. Here's the code below.

The clock period is set with a local variable called PULSE_WIDTH.

Again, very simple and basic, but making progress.

We've been studying a book by U. Meyer-Baese called "Digital Signal Processing with Field Programmable Gate Arrays". There's a section on Costas Loops that reiterates what Bob McGwier said about phase and gain sensitivity. So, we're on the right track!

We'll most likely start storing these files on the website. Another place they will live, as a project, will be at the Open Cores website, where lots of open source HDL projects are hosted.

----------------------------------------------------------------------------------
-- Company: Optimized Tomfoolery
-- Engineer: Michelle Thompson
--
-- Create Date:    09:40:09 05/27/2010
-- Design Name: BERT
-- Module Name:    clock - Behavioral
-- Project Name: MEP
-- Target Devices:
-- Tool versions:
-- Description: Clock that drives d flip flop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock is
 generic (PULSE_WIDTH : TIME := 20ns);
    Port ( clock : out  STD_LOGIC);
end clock;
architecture Behavioral of clock is
begin
 Gen_Clock:
 process
  constant PERIOD: TIME := 2*PULSE_WIDTH;
 begin
  clock <= '1' after PULSE_WIDTH,
     '0' after PERIOD;
  wait for PERIOD;
 end process Gen_Clock;
end Behavioral;
----------------------------------------------------------------------------------

more soon, 
-Michelle W5NYV
Potestatem obscuri lateris nescis.