I have a VHDL implementation of the IQ phase and gain correction algorithm
working. This implementation isn't synthesizeable in logic (yet), but it will be
as soon as I figure out why signed multiplication gives the wrong result.
Since I have a version that is working (with some of the internal math done with
variables instead of registers) I'm taking the opportunity to work on gain and
phase lock and the creation of "corrected" I and Q signals.
I is passed along with a filter delay, and corrected Q is passed along.
This part needs to be done regardless of how the internals of the correction
block are implemented.
If you haven't visited the opencores.com site, then you might want to drop by
and check it out. We're in there!
IQ Phase and Gain Correction is the name of the project and our page is
I'll have today's cut of code up there after a celebratory lunch.
More soon (phase and gain lock signals in progress)
Potestatem obscuri lateris nescis.