Gain correction algorithm. I'll publish a cut of it in a separate email.
What I wanted to share was a few very brief observations about learning VHDL.
The actual description of what you want to accomplish may take much less time
than constructing a test that really tests what you have designed.
VHDL projects are usually broken down into components, which are the blocks that
implement your function, and testbenches, which (as the name implies) are
constructed logic that proves the block that implements the function does
what you intended to tell it to do.
So far, the proportion of time spent designing the block that implements the
function vs. designing the testbench for it is about 4:1. I don't expect this to
change throughout the remaining 5 weeks of the course.
VHDL is very strongly typed, and most of the issues I've had so far have been
getting used to this. Once you get the hang of it, it does get better, and makes
it easy to catch most errors.
We're using the student version of Aldec Active-HDL for the development
environment. I have to say I like it a bit more than the Xilinx ISE webpack, but
the differences are minor, and the Aldec license is good for only a year at a
More soon!-Michelle W5NYV
Potestatem obscuri lateris nescis.