I have a report.
While pedaling away at the gym in continuing efforts to not be fat, I admitted to feeling kind of down in the dumps about tools for MEP. I was feeling somewhat chumpish because it isn't reasonable to ask participants to spend thousands of dollars on MATLAB, Simulink, etc. And, it's easy to start blaming the lack of tools for lack of progress.
After given a pep talk concerning open source, I installed Octave (open source alternative to MATLAB) and found something called ScicosLabGtk (open source alternative to Simulink). I installed it too.
After a couple hours of reading tutorials, Octave is less scary and more useful than I expected.
The practice problem I selected was to implement the constraint length 7, rate 1/2 code used on the Voyager space program.
Also, some time back Roger AD5T sent an article from the June IEEE Communications journal about 5 port devices. I'm asking around to see if we can build some of these. The center frequency is 4.5GHz, and the bandwidth is a whopping 3GHz. The RF and LO are the inputs, and the various combinations thereof comprise 3 outputs. Power detectors are used to make an output signal. There are no mixers. It's kind of whacky, but the article showed working hardware that I'd like to duplicate and evaluate. That sort of bandwidth, by my reckoning, includes both MEP bands at 3.4 and 5.8GHz.
I can't attach the article due to copyright issues, but I am working on getting it reinterpreted to share on mep-dev. More soon!
Here's an early snapshot of the Octave practice problem included below. It's not (yet) elegant.
I'm going to do this problem in Octave, then implement it in VHDL using the free version of the Xilinx tools. Remember, version 12 is out, so install and/or upgrade. That will be our baseline VHDL tool for MEP. The idea is to have a mathematical model of the things we do in Octave, and a model in VHDL. The two implementations should agree.
# Voyager Encoder
# we have a 7-bit register with taps on top
# at 0, 2, 3, 5, 6 (inverter)
# and taps on the bottom
# at 0, 1, 2, 3, 6 (noninverted)
# signals are multiplexed at the end to get the result.
taps_inverted_side = [1, 0, 1, 1, 0, 1, 1]
taps_noninverted_side = [1, 1, 1, 1, 0, 0, 1]
register = zeros(1,7)
register(1,1) = 1
# To access the item at row i and column j, just use the command register(i, j)
# set up a loop
# !!!this needs to be made to work for arbitrary length input
i = [1:10]
for Clock_cycle = i
# !!!make this generic in the future. Gate the xors with the taps from above by using AND.
inverted_side = !xor(register(1,7),(xor(register(1,6),(xor(register(1,4),(xor(register(1,1),register(1,3))))))))
noninverted_side = xor(register(1,7),(xor(register(1,4),(xor(register(1,3),(xor(register(1,1),register(1,2))))))))
#print what is in our register
#advance values of register
register(1,7) = register(1,6)
register(1,6) = register(1,5)
register(1,5) = register(1,4)
register(1,4) = register(1,3)
register(1,3) = register(1,2)
register(1,2) = register(1,1)
register(1,1) = 0