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LinkedIn Hi Jeffrey, Your LinkedIn password has been reset successfully. Thank you, The LinkedIn Team This email was intended for Jeffrey Pawlan. Learn why we included this. © 2012, LinkedIn Corporation. 2029 Stierlin Ct. Mountain View, CA 94043, USA Friday, January 27, 2012 Heads-up Display Proposal for GNU Radio (and MEP) Sunday, August 28, 2011 Six-Ports Paper appearing in The Proceedings of Microwave Update 2011. It's about the basics of six-port theory, with an explanation of six-ports as modulator and demodulator. Saturday, August 27, 2011 Six-port article for MUD Greetings all! This October, a six-port paper will be included in the Proceedings of Microwave Update 2011. If you read the old six-port paper, this is a major revision and expansion.  http://www.delmarnorth.com/microwave/newsletters/sixportmodel.pdf Next step: building six-ports with the recently received couplers and dividers, at 1.2GHz in order to experiment with local amateur DTV.  https://plus.google.com/114254220048556407553/posts/MVTkLTbNuXB I'm hoping that experiments at 1.2GHz will produce enough know-how to make a reliable recipe, and then that recipe can be used at 3 and 5 GHz. I'll be out of town until September 7th. My three children will be back in school on Monday, and I'll begin to have a lot more time to help out on MEP and related experiments. Summer is a bit more challenging in terms of having uninterrupted time. This list is intended to support and encourage amateur microwave engineering projects, so please speak up with ideas, comments, critiques, proposals and plans.  Looking forward to the fall,  -Michelle W5NYV Sit vis vobiscum! Monday, August 8, 2011 Qt4 built, building a GUI for SDRs After reinstalling Xcode, Qt4 installed from the repository. This is the recommended way to build GUIs for MEP. Thanks to Jacob for highlighting Qt4 and recommending a book. If you're interested in building the GUI, then install Qt and speak up!  :+) Tom Rondeau had some very nice things to say about a model-view-controller architecture-for-SDR letter I wrote him and fred harris a couple months back. The response got me thinking about exactly how one would want to partition tasks for an SDR, and how those partitions could improve the user experience and user interface. Model-view-controller type software writing can be very user (and user-interface) focused. What I'd like to look at is how to best write a GUI for SDR. While the application is MEP, I'm looking for generalizations that will be useful to others. What do you all think? -Michelle W5NYV Friday, July 22, 2011 Numbering Scheme, looking for hybrid couplers and dividers, and MUD? Hi everyone!  Here's a document about the numbering scheme in the IQ Gain and Phase Correction Filter.  I bought the first set of parts for experimenting with six-port structures. Two 90 degree hybrid couplers off eBay. The target application is DVB amateur television. There's a repeater near me for DVB ATV. The frequency of interest for this experiment is 1.2GHz. If you have any 90 degree hybrid couplers or power dividers for this frequency, and are willing to donate them to the cause, let me know! I'm looking for at least 4 more couplers and 2 dividers (0 degree phase, equal power dividers).  Does anyone have any plans to attend Microwave Update in Connecticut this year?    -Michelle W5NYV Thursday, June 2, 2011 FPGAs in space Article from EE Times about FPGAs in a cubesat project. http://www.eetimes.com/design/military-aerospace-design/4216480/High-performance-FPGAs-take-flight-in-microsatellites?cid=NL_ProgrammableLogic&Ecosystem=programmable-logic  -Michelle W5NYV Potestatem obscuri lateris nescis. Saturday, May 28, 2011 VHDL implementation compared to MATLAB model - overall success Overview of successful results with synthesizeable VHDL implementation. Comparison with MATLAB results. -Michelle W5NYV Thursday, May 19, 2011 "What's Up With ARM" Here's an opinion piece about the current state of Linux development on ARM. I thought it was interesting, largely agree with the author, and wanted to share it with you guys. http://www.linux.com/news/featured-blogs/171-jonathan-corbet/445344-whats-up-with-arm Having got the beagleboard lab back up and running after the extended tour of duty doing VHDL, I find that it is very true that getting Linux working on ARM can be much more "some assembly required" than, say, a desktop. It's well worth it, considering how powerful the ARM family is. In order to develop something useful for MEP on ARM, there is quite a bit of slogging to do through various rough edges. When experimenting with cameras and video output, nothing ever really "quite worked", and the variety and duplication mentioned in the article were in full evidence. The current Angstrom build I'm working with was obtained from the Narcissus Angstrom image builder. I used this because I simply could not get the demo build of Angstrom to cleanly update from the package server. This sort of obstacle can be really frustrating. Here is the link to generate a build of Angstrom: http://narcissus.angstrom-distribution.org/ This image boots, but I haven't gotten much farther than launching Firefox. More soon! -Michelle W5NYV Monday, May 9, 2011 updated synthesizeable VHDL block - progress Here is updated VHDL code for the IQ Gain and Phase Correction filter. I'm working with an adjusted numbering scheme in signed arithmetic to correct an overflow problem (thanks to KB5MU, who helped identify).  This implementation, which is designed to be synthesizeable, is beginning to function as intended. There is a factor of two error, but the compiled block outputs I and Q. With some data visualization, these might prove to be a passed-through I and phase corrected Q at the output, with a massive gain overcorrection. I'll check that tomorrow!  -Michelle W5NYV Friday, April 22, 2011 VHDL update - IQ Gain and Phase correction, next blocks Hi everyone! I'm back to work on the VHDL after an interruption for a DXpedition to Curaçao, spring break shennanigans, and photographing a wedding. I took the entity, architecture, and the testbench from the variable (non-synthesizeable) version, and started a new workspace. The goal is to get the register-based version working. When last I attempted this, I got incorrect results from multiplication. I'm making another run at it to get this filter ready for synthesis (when it's put into an FPGA, instead of just working as a mathematical model). If you're interested in working on VHDL for MEP, there is PLENTY of opportunity. It doesn't even have to be VHDL. If you work in Verilog, and can synthesize the block, then go for it. I'm approaching this like a slow-growing bacteria that spreads to adjacent blocks in the petri dish. The next block upstream is automatic gain control. I've read the wikipedia article about AGC, but that's about as far as I've gotten. Article here: http://en.wikipedia.org/wiki/Automatic_gain_control Does anyone on the list have any experience with AGC design or analysis? I understand why AGC is important, and I think I understand the trade-offs. I'm not sure quite yet how to design a block that achieves AGC. Right now, the AGC is modeled in the IQ correction block by simply dividing the incoming values of the signals by the maximum expected value. I'd like to replace that modeling with a block that does the AGC before the samples are delivered to the filter. The next block downstream is, I believe, the demodulator. I have attached a pdf with the current snapshot of the IQ Gain and Phase code. More soon,-Michelle W5NYV Potestatem obscuri lateris nescis. Saturday, March 5, 2011 IQ Correction VHDL update Greetings everyone, I have a VHDL implementation of the IQ phase and gain correction algorithm working. This implementation isn't synthesizeable in logic (yet), but it will be as soon as I figure out why signed multiplication gives the wrong result. Since I have a version that is working (with some of the internal math done with variables instead of registers) I'm taking the opportunity to work on gain and phase lock and the creation of "corrected" I and Q signals. I is passed along with a filter delay, and corrected Q is passed along. This part needs to be done regardless of how the internals of the correction block are implemented. If you haven't visited the opencores.com site, then you might want to drop by and check it out. We're in there! IQ Phase and Gain Correction is the name of the project and our page is http://opencores.com/project,iqcorrection I'll have today's cut of code up there after a celebratory lunch.    More soon (phase and gain lock signals in progress) -Michelle W5NYV Potestatem obscuri lateris nescis. Tuesday, February 22, 2011 Package that makes normally distributed random numbers from uniform numbers In order to be able to have normal distribution noise, I made a package that takes the uniform distribution random numbers and uses the central limit theorem to give an (approximately) normal distribution. Here's the package: library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use work.random_int.all; --by MEP 22 February 2011 --usage: --this is a function, which means it can be on the right-hand side --of an assignment. It returns a mean-zero random number from a --normal distribution. The argument is a real number that indicates --the standard deviation desired. -- --random_noise(sigma); -- package normal_distribution_random_noise is function random_noise ( sigma : real) return real; end package normal_distribution_random_noise; package body normal_distribution_random_noise is function random_noise ( sigma : real ) return real is --variables variable u_noise: real; --uniform distribution noise variable n_noise: real := 0.0; --normal distribution noise variable seed1 : positive; variable seed2 : positive; begin --obtain a uniformly distributed random number uniform(seed1, seed2, u_noise); --report "Random uniform noise is " & real'image(u_noise) & "."; for normal_count in 0 to 12 loop --Turn the uniform distributed number --into a normally distributed number --by using the central limit theorem. --Make it mean zero and make it have --the range of the uniform numbers --that it is composed from. n_noise := n_noise + u_noise; end loop; n_noise := n_noise - (0.5)*(real(12)); --normal distribution with a mean of zero --report "Random normal noise is " & real'image(n_noise) & "."; n_noise := n_noise/(real(12)); --report "Random normal noise using range of uniform is " & real'image(n_noise) & "."; n_noise := sigma*n_noise; return n_noise; end function random_noise; end package body normal_distribution_random_noise; Package that creates I and Q samples to test the IQ Correction block library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use work.normal_distribution_random_noise.all; --by MEP 22 February 2011 --usage: --these are functions, which means they can be on the right-hand side --of an assignment. These functions create an I and Q sample. --The arguments are --a natural number standing for the index of the sample, --a real number that provides a way to have many samples per period, --a real number standing for the standard deviation of the normally distributed noise added to the sample, --a real number standing for the amplitude of the signal, --a natural number indicating the width of the vector holding the returned value, --a real number indicating the gain error of Q with respect to I, --and a real number indicating the phase error of Q with respect to I -- --create_I_sample(n_dat, freq, sgma, amplitude, return_width); --create_Q_sample(n_dat, freq, sgma, amplitude, return_width, e1, a1); -- package create_sample is function create_I_sample( n_dat : integer; freq : real; sgma : real; amplitude : real; return_width : natural) return signed; function create_Q_sample( n_dat : integer; freq : real; sgma : real; amplitude : real; return_width : natural; --x1_tb'LENGTH e1 : real; --gain error a1 : real) --phase error return signed; end package create_sample; package body create_sample is function create_I_sample( n_dat : integer; freq : real; sgma : real; amplitude : real; return_width : natural) --x1_tb'LENGTH return signed is variable local_x1 : real; variable int_x1: integer; variable returned_x1 : signed(return_width downto 0); begin local_x1 := amplitude*sin(2.0*math_pi*(real(n_dat))*freq) + random_noise(sgma); --report "local_x1 inside CREATE_I_SAMPLE function is " & real'image(local_x1) & "."; --AGC scaling. Scaling factor is maximum value the signal can take. local_x1 := local_x1/(1.11); --report "local_x1 after AGC inside CREATE_I_SAMPLE function is " & real'image(local_x1) & "."; int_x1 := integer(trunc(local_x1*((2.0**31.0)-1.0))); --scaled --report "integer version of x1 inside CREATE_I_SAMPLE function is " & integer'image(int_x1) & "."; returned_x1 := (to_signed(int_x1, return_width+1)); return returned_x1; end function; function create_Q_sample( n_dat : integer; freq : real; sgma : real; amplitude : real; return_width : natural; --x1_tb'LENGTH e1 : real; --gain error a1 : real) return signed is variable local_y1 : real; variable int_y1: integer; variable returned_y1 : signed(return_width downto 0); begin local_y1 := amplitude*(1.0 + e1)*cos(2.0*math_pi*(real(n_dat))*freq + a1) + random_noise(sgma); --report "local_y1 first created CREATE_Q_SAMPLE function is " & real'image(local_y1) & "."; --AGC scaling. Scaling factor is maximum value the signal can take. local_y1 := local_y1/(1.11); --report "local_y1 after AGC inside CREATE_Q_SAMPLE function is " & real'image(local_y1) & "."; int_y1 := integer(trunc(local_y1*((2.0**31.0)-1.0))); --scaled --report "integer version of y1 inside CREATE_Q_SAMPLE function is " & integer'image(int_y1) & "."; returned_y1 := (to_signed(int_y1, return_width+1)); return returned_y1; end function; end package body create_sample; IQ Phase Gain Correction testbench library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use work.normal_distribution_random_noise.all; use work.create_sample.all; entity IQGainPhaseCorrection_testbench is end entity; architecture IQGainPhaseCorrection_testbench_arch of IQGainPhaseCorrection_testbench is --declare the DUT as a component. component IQGainPhaseCorrection is generic(width :natural); port( clk :in std_logic; x1 :in signed(width downto 0); y1 :in signed(width downto 0); gain_error :out signed(width downto 0); gain_lock :out bit; phase_error :out signed(width downto 0); phase_lock :out bit; corrected_x1 :out signed(width downto 0); corrected_y1 :out signed(width downto 0) ); end component; --provide signals to run the DUT. signal clk_tb : std_logic := '0'; signal clk_tb_delayed : std_logic := '0'; signal x1_tb : signed(31 downto 0); signal y1_tb : signed(31 downto 0); signal gain_error_tb : signed(31 downto 0); signal gain_lock_tb : bit; signal phase_error_tb : signed(31 downto 0); signal phase_lock_tb : bit; signal corrected_x1_tb : signed(31 downto 0); signal corrected_y1_tb : signed(31 downto 0); begin --connect the testbench signal to the component DUT:IQGainPhaseCorrection generic map( width => 31 ) port map( clk => clk_tb_delayed, x1 => x1_tb, y1 => y1_tb, gain_error => gain_error_tb, gain_lock => gain_lock_tb, phase_error => phase_error_tb, phase_lock => phase_lock_tb, corrected_x1 => corrected_x1_tb, corrected_y1 => corrected_y1_tb ); --create I and Q. MTreseler says, "sin in vhdl I use use ieee.math_real.all and cast to integer." CREATE_I_Q_SAMPLES: process (clk_tb) is --for both I and Q variable n_dat : integer := 0; variable freq : real := 0.03; --relative frequency variable sgma : real :=0.01; --sigma of noise variable amplitude : real := 1.0; --amplitude --for Q variable e1 : real := 0.1; --gain error variable a1 : real := (10.0*math_pi)/180.0; --phase error of 10 degrees begin if (clk_tb'event and clk_tb = '1') then x1_tb <= create_I_sample(n_dat, freq, sgma, amplitude, 31); y1_tb <= create_Q_sample(n_dat, freq, sgma, amplitude, 31, e1, a1); n_dat := n_dat + 1; end if; end process CREATE_I_Q_SAMPLES; DRIVE_CLOCK:process begin wait for 50 ns; clk_tb <= not clk_tb; clk_tb_delayed <= not clk_tb_delayed after 1 ns; end process; end IQGainPhaseCorrection_testbench_arch; IQ Phase Gain Correction architecture architecture IQGainPhaseCorrection_beh of IQGainPhaseCorrection is --signal declarations --phase error estimate accumulator signal reg_1:signed(width downto 0) := (others => '0'); --gain error estimate accumulator signal reg_2:signed(width downto 0) := (0 => '1', others => '0'); --Phase Offset Adjustment Applied to y1 signal y2:signed(width downto 0) := (others => '0'); --Gain and Phase Adjustment Applied to y1 signal y3:signed(2*width+1 downto 0) := (others => '0'); signal x1y2:signed(2*width+1 downto 0):= (others => '0'); signal mu_1:signed(width downto 0):= (others => '0'); signal x1x1y3y3:signed(width downto 0):= (others => '0'); signal mu_2:signed(width downto 0):= (others => '0'); signal reg_1x1:signed(2*width+1 downto 0):= (others => '0'); signal y3y3: signed(4*width+3 downto 0):= (others => '0'); signal x1x1: signed(2*width+1 downto 0):= (others => '0'); begin correction : process (clk) is begin if clk'event and clk = '1' then --phase error estimate, step size set to 0.000244 --which is achieved with a shift right by 12. reg_1x1 <= reg_1 * x1; --clock 0 y2 <= y1 - reg_1x1(2*width+1 downto width+1); --clock 1 x1y2 <= x1 * y2; --clock 2 mu_1 <= shift_right(x1y2(2*width+1 downto width+1),12); --step size applied. --clock 3 reg_1 <= reg_1 + mu_1; --clock 4 phase_error <= reg_1; --update phase error estimate. --clock 5 --gain error estimate, step size set to 0.000122 --which is achieved with a shift right by 13. y3 <= y2 * reg_2; --clock 0 --63 downto 0 n*32 - 1, n = 2 x1x1 <= x1 * x1; --clock 0 --63 downto 0 y3y3 <= y3 * y3; --clock 1 --127 downto 0 n*32 -1, n = 4 to n = 3 x1x1y3y3 <= (abs(x1x1(2*width+1 downto width+1))) - (abs(y3y3(4*width+3 downto 3*width+3))); --clock 2 mu_2 <= shift_right(x1x1y3y3, 13); --clock 3 reg_2 <= reg_2 + mu_2; --clock 4 gain_error <= reg_2; --update gain error estimate. --clock 5 end if; end process; end IQGainPhaseCorrection_beh; IQ Phase Gain Correction entity library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith; use ieee.numeric_std.all; entity IQGainPhaseCorrection is generic(width:natural); port( clk :in std_logic; x1 :in signed(width downto 0); y1 :in signed(width downto 0); gain_error :out signed(width downto 0); gain_lock :out bit; phase_error :out signed(width downto 0); phase_lock :out bit; corrected_x1 :out signed(width downto 0); corrected_y1 :out signed(width downto 0) ); end IQGainPhaseCorrection; IQ Phase and Gain Correction - Testbench Below is the testbench for the IQ Phase and Gain Correction. As you can see, there's a lot more going on in the testbench than in the block for the algorithm. This is because the testbench has to generate the test signals and provide the clock and establish the various settings for the test, and that all adds up in this case to more lines of code. On the list of improvements is to move the I and Q signal creation into a procedure. This encapsulates code and will make the testbench a lot more readable. Another obvious improvement is to figure out exactly why the gain correction isn't working yet. More soon, -Michelle W5NYV library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; entity IQGainPhaseCorrection_testbench is end entity; architecture IQGainPhaseCorrection_testbench_arch of IQGainPhaseCorrection_testbench is --declare the DUT as a component. component IQGainPhaseCorrection is generic(width :natural); port( clk :in std_logic; x1 :in signed(width downto 0); y1 :in signed(width downto 0); gain_error :out signed(width downto 0); gain_lock :out bit; phase_error :out signed(width downto 0); phase_lock :out bit; corrected_x1 :out signed(width downto 0); corrected_y1 :out signed(width downto 0) ); end component; --provide signals to run the DUT. signal clk_tb : std_logic := '0'; signal x1_tb : signed(31 downto 0); signal y1_tb : signed(31 downto 0); signal gain_error_tb : signed(31 downto 0); signal gain_lock_tb : bit; signal phase_error_tb : signed(31 downto 0); signal phase_lock_tb : bit; signal corrected_x1_tb : signed(31 downto 0); signal corrected_y1_tb : signed(31 downto 0); begin --connect the testbench signal to the component DUT:IQGainPhaseCorrection generic map( width => 31 ) port map( clk => clk_tb, x1 => x1_tb, y1 => y1_tb, gain_error => gain_error_tb, gain_lock => gain_lock_tb, phase_error => phase_error_tb, phase_lock => phase_lock_tb, corrected_x1 => corrected_x1_tb, corrected_y1 => corrected_y1_tb ); --create x1 and y1. MTreseler says, "sin in vhdl I use use ieee.math_real.all and cast to integer." CREATE_X1_I: process variable angle : real; variable local_x1 : real; variable sgma : real :=0.01; --sigma of noise variable amplitude : real := 1.0; --amplitude variable freq : real := 0.03; --relative frequency variable u_noise: real; --uniform distribution noise variable n_noise: real := 0.0; --normal distribution noise variable seed1 : positive := 10; variable seed2 : positive := 200; --loop controls variable make_normal_count : integer := 12; variable n_dat : integer := 4; variable int_x1: integer; begin for n_dat_count in 0 to n_dat loop --make a random number uniform(seed1, seed2, u_noise); report "Random uniform noise in I creation is " & real'image(u_noise) & "."; for normal_count in 0 to make_normal_count loop --turn the uniform distributed number --into a normally distributed number --by using the central limit theorem. n_noise := n_noise + u_noise; end loop; n_noise := n_noise - (0.5)*(real(make_normal_count)); --normal distribution with a mean of zero report "Random normal noise in I creation is " & real'image(n_noise) & "."; n_noise := n_noise/(real(make_normal_count)); --max values reduced? report "Random normal noise (normalized?) in I creation is " & real'image(n_noise) & "."; local_x1 := amplitude*cos(2.0*math_pi*(real(n_dat_count))*freq) + sgma*(n_noise); --local_x1 := cos(2.0*math_pi*(real(n_dat_count))*freq); --simpler version --AGC scaling local_x1 := local_x1/(1.01); report "local_x1 is " & real'image(local_x1) & "."; --x1_tb <= local_x1; --somehow get real turned into signed. -- 1. rescale to 0..(nearly)4096, find integer part --int_x1 := INTEGER(TRUNC(local_x1*4294967296.0)); -- from random_vector int_x1 := integer(trunc(local_x1*(2.0**31.0))); --scaled report "integer version of x1 is " & integer'image(int_x1) & "."; -- 2. convert to signed x1_tb <= (to_signed(int_x1, x1_tb'LENGTH)); end loop; wait; end process CREATE_X1_I; CREATE_Y1_Q: process variable angle : real; variable local_y1 : real; variable e1 : real := 0.1; --gain error variable a1 : real := (10.0*math_pi)/180.0; --phase error of 10 degrees variable sgma : real := 0.01; --sigma of noise variable amplitude : real := 1.0; --amplitude variable freq : real := 0.03; --relative frequency variable u_noise: real; --uniformly distributed noise variable n_noise: real := 0.0; --normally distributed noise variable seed1 : positive := 1; variable seed2 : positive := 2; --loop controls variable make_normal_count : integer := 12; variable n_dat : integer := 4; variable int_y1: integer; begin for n_dat_count in 0 to n_dat loop --make a random number uniform(seed1, seed2, u_noise); report "Random uniform noise in I creation is " & real'image(u_noise) & "."; for normal_count in 0 to make_normal_count loop --turn the uniform distributed number --into a normally distributed number --by using the central limit theorem. n_noise := n_noise + u_noise; end loop; n_noise := n_noise - (0.5)*(real(make_normal_count)); n_noise := n_noise/(real(make_normal_count)); --reduce size of noise report "Random normal noise in I creation is " & real'image(n_noise) & "."; n_noise := n_noise/(real(make_normal_count)); --max values reduced? report "Random normal noise (normalized?) in I creation is " & real'image(n_noise) & "."; local_y1 := amplitude*(1.0 + e1)*cos(2.0*math_pi*(real(n_dat_count))*freq + a1) + sgma*(n_noise); --AGC scaling local_y1 := local_y1/(1.01); --int_y1 := INTEGER(TRUNC(local_y1*4294967296.0)); -- from random_vector int_y1 := integer(trunc(local_y1*(2.0**31.0))); --scaled report "integer version of y1 is " & integer'image(int_y1) & "."; -- 2. convert to signed y1_tb <= (to_signed(int_y1, y1_tb'LENGTH)); end loop; wait; end process CREATE_Y1_Q; DRIVE_CLOCK:process begin clk_tb <= not clk_tb; wait for 50 ns; end process; end IQGainPhaseCorrection_testbench_arch; IQ Phase and Gain Correction I'm working on the IQ Phase and Gain Correction VHDL implementation today. Here is the entity and architecture below. In the testbench, the phase correction works (with some amount of oscillation), but the gain correction increases without bound. Trying to track that down today. I'll post the testbench next in a separate email. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith; use ieee.numeric_std.all; entity IQGainPhaseCorrection is generic(width:natural); port( clk :in std_logic; x1 :in signed(width downto 0); y1 :in signed(width downto 0); gain_error :out signed(width downto 0); gain_lock :out bit; phase_error :out signed(width downto 0); phase_lock :out bit; corrected_x1 :out signed(width downto 0); corrected_y1 :out signed(width downto 0) ); end IQGainPhaseCorrection; architecture IQGainPhaseCorrection_beh of IQGainPhaseCorrection is --signal declarations --phase error estimate accumulator signal reg_1:signed(width downto 0) := (others => '0'); --gain error estimate accumulator signal reg_2:signed(width downto 0) := (0 => '1', others => '0'); --Phase Offset Adjustment Applied to y1 signal y2:signed(width downto 0) := (others => '0'); --Gain and Phase Adjustment Applied to y1 signal y3:signed(2*width+1 downto 0) := (others => '0'); signal x1y2:signed(2*width+1 downto 0):= (others => '0'); signal mu_1:signed(width downto 0):= (others => '0'); signal x1x1y3y3:signed(width downto 0):= (others => '0'); signal mu_2:signed(width downto 0):= (others => '0'); signal reg_1x1:signed(2*width+1 downto 0):= (others => '0'); signal y3y3: signed(4*width+3 downto 0):= (others => '0'); signal x1x1: signed(2*width+1 downto 0):= (others => '0'); begin correction : process (clk) is begin if clk'event and clk = '1' then --phase error estimate, step size set to 0.000244 --which is achieved with a shift right by 12. reg_1x1 <= reg_1 * x1; --clock 0 y2 <= y1 - reg_1x1(2*width+1 downto width+1); --clock 1 x1y2 <= x1 * y2; --clock 2 mu_1 <= shift_right(x1y2(2*width+1 downto width+1),12); --step size applied. --clock 3 reg_1 <= reg_1 + mu_1; --clock 4 phase_error <= reg_1; --update phase error estimate. --clock 5 --gain error estimate, step size set to 0.000122 --which is achieved with a shift right by 13. y3 <= y2 * reg_2; --clock 0 --63 downto 0 n*32 - 1, n = 2 x1x1 <= x1 * x1; --clock 0 --63 downto 0 y3y3 <= y3 * y3; --clock 1 --127 downto 0 n*32 -1, n = 4 to n = 3 x1x1y3y3 <= (abs(x1x1(2*width+1 downto width+1))) - (abs(y3y3(4*width+3 downto 3*width+3))); --clock 2 mu_2 <= shift_right(x1x1y3y3, 13); --clock 3 reg_2 <= reg_2 + mu_2; --clock 4 gain_error <= reg_2; --update gain error estimate. --clock 5 end if; end process; end IQGainPhaseCorrection_beh; Thursday, February 17, 2011 VHDL experience so far I'm halfway through the VHDL class and well into implementing the IQ Phase and Gain correction algorithm. I'll publish a cut of it in a separate email. What I wanted to share was a few very brief observations about learning VHDL. The actual description of what you want to accomplish may take much less time than constructing a test that really tests what you have designed. VHDL projects are usually broken down into components, which are the blocks that implement your function, and testbenches, which (as the name implies) are constructed logic that proves the block that implements the function does what you intended to tell it to do. So far, the proportion of time spent designing the block that implements the function vs. designing the testbench for it is about 4:1. I don't expect this to change throughout the remaining 5 weeks of the course.  VHDL is very strongly typed, and most of the issues I've had so far have been getting used to this. Once you get the hang of it, it does get better, and makes it easy to catch most errors.   We're using the student version of Aldec Active-HDL for the development environment. I have to say I like it a bit more than the Xilinx ISE webpack, but the differences are minor, and the Aldec license is good for only a year at a time. More soon!-Michelle W5NYV Potestatem obscuri lateris nescis. Subscribe to: Posts (Atom)