VHDL update - IQ Gain and Phase correction, next blocks

Hi everyone! I'm back to work on the VHDL after an interruption for a DXpedition
to Curaçao, spring break shennanigans, and photographing a wedding.

I took the entity, architecture, and the testbench from the variable
(non-synthesizeable) version, and started a new workspace. The goal is to get
the register-based version working. When last I attempted this, I got incorrect
results from multiplication. I'm making another run at it to get this filter
ready for synthesis (when it's put into an FPGA, instead of just working as a
mathematical model).

If you're interested in working on VHDL for MEP, there is PLENTY of opportunity.
It doesn't even have to be VHDL. If you work in Verilog, and can synthesize the
block, then go for it.

I'm approaching this like a slow-growing bacteria that spreads to adjacent
blocks in the petri dish. The next block upstream is automatic gain control.
I've read the wikipedia article about AGC, but that's about as far as I've
gotten.

Article here:
http://en.wikipedia.org/wiki/Automatic_gain_control

Does anyone on the list have any experience with AGC design or analysis? I
understand why AGC is important, and I think I understand the trade-offs. I'm
not sure quite yet how to design a block that achieves AGC. Right now, the AGC
is modeled in the IQ correction block by simply dividing the incoming values of
the signals by the maximum expected value.

I'd like to replace that modeling with a block that does the AGC before the
samples are delivered to the filter.

The next block downstream is, I believe, the demodulator.

I have attached a pdf with the current snapshot of the IQ Gain and Phase code.

More soon,-Michelle W5NYV

Potestatem obscuri lateris nescis.