FPGAs in space

Article from EE Times about FPGAs in a cubesat project.

http://www.eetimes.com/design/military-aerospace-design/4216480/High-performance-FPGAs-take-flight-in-microsatellites?cid=NL_ProgrammableLogic&Ecosystem=programmable-logic

 -Michelle W5NYV

Potestatem obscuri lateris nescis.

VHDL implementation compared to MATLAB model - overall success

Overview of successful results with synthesizeable VHDL implementation.
Comparison with MATLAB results.
-Michelle W5NYV

"What's Up With ARM"

Here's an opinion piece about the current state of Linux development on ARM. I
thought it was interesting, largely agree with the author, and wanted to share
it with you guys.

http://www.linux.com/news/featured-blogs/171-jonathan-corbet/445344-whats-up-with-arm

Having got the beagleboard lab back up and running after the extended tour of
duty doing VHDL, I find that it is very true that getting Linux working on ARM
can be much more "some assembly required" than, say, a desktop. It's well worth
it, considering how powerful the ARM family is.

In order to develop something useful for MEP on ARM, there is quite a bit of
slogging to do through various rough edges. When experimenting with cameras and
video output, nothing ever really "quite worked", and the variety and
duplication mentioned in the article were in full evidence.

The current Angstrom build I'm working with was obtained from the Narcissus
Angstrom image builder. I used this because I simply could not get the demo
build of Angstrom to cleanly update from the package server. This sort of
obstacle can be really frustrating.

Here is the link to generate a build of Angstrom:
http://narcissus.angstrom-distribution.org/

This image boots, but I haven't gotten much farther than launching Firefox.

More soon!
-Michelle W5NYV

updated synthesizeable VHDL block - progress

Here is updated VHDL code for the IQ Gain and Phase Correction filter.

I'm working with an adjusted numbering scheme in signed arithmetic to correct an
overflow problem (thanks to KB5MU, who helped identify). 

This implementation, which is designed to be synthesizeable, is beginning to
function as intended. There is a factor of two error, but the compiled block
outputs I and Q.

With some data visualization, these might prove to be a passed-through I and
phase corrected Q at the output, with a massive gain overcorrection. I'll check
that tomorrow!

 -Michelle W5NYV

VHDL update - IQ Gain and Phase correction, next blocks

Hi everyone! I'm back to work on the VHDL after an interruption for a DXpedition
to Curaçao, spring break shennanigans, and photographing a wedding.

I took the entity, architecture, and the testbench from the variable
(non-synthesizeable) version, and started a new workspace. The goal is to get
the register-based version working. When last I attempted this, I got incorrect
results from multiplication. I'm making another run at it to get this filter
ready for synthesis (when it's put into an FPGA, instead of just working as a
mathematical model).

If you're interested in working on VHDL for MEP, there is PLENTY of opportunity.
It doesn't even have to be VHDL. If you work in Verilog, and can synthesize the
block, then go for it.

I'm approaching this like a slow-growing bacteria that spreads to adjacent
blocks in the petri dish. The next block upstream is automatic gain control.
I've read the wikipedia article about AGC, but that's about as far as I've
gotten.

Article here:
http://en.wikipedia.org/wiki/Automatic_gain_control

Does anyone on the list have any experience with AGC design or analysis? I
understand why AGC is important, and I think I understand the trade-offs. I'm
not sure quite yet how to design a block that achieves AGC. Right now, the AGC
is modeled in the IQ correction block by simply dividing the incoming values of
the signals by the maximum expected value.

I'd like to replace that modeling with a block that does the AGC before the
samples are delivered to the filter.

The next block downstream is, I believe, the demodulator.

I have attached a pdf with the current snapshot of the IQ Gain and Phase code.

More soon,-Michelle W5NYV

Potestatem obscuri lateris nescis.

IQ Correction VHDL update

Greetings everyone,

I have a VHDL implementation of the IQ phase and gain correction algorithm
working. This implementation isn't synthesizeable in logic (yet), but it will be
as soon as I figure out why signed multiplication gives the wrong result.

Since I have a version that is working (with some of the internal math done with
variables instead of registers) I'm taking the opportunity to work on gain and
phase lock and the creation of "corrected" I and Q signals.

I is passed along with a filter delay, and corrected Q is passed along.

This part needs to be done regardless of how the internals of the correction
block are implemented.

If you haven't visited the opencores.com site, then you might want to drop by
and check it out. We're in there!

IQ Phase and Gain Correction is the name of the project and our page is
http://opencores.com/project,iqcorrection

I'll have today's cut of code up there after a celebratory lunch. 
 
More soon (phase and gain lock signals in progress)
-Michelle W5NYV

Potestatem obscuri lateris nescis.

Package that makes normally distributed random numbers from uniform numbers

In order to be able to have normal distribution noise, I made a package that
takes the uniform distribution random numbers and uses the central limit theorem
to give an (approximately) normal distribution. Here's the package:

library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.random_int.all;

--by MEP 22 February 2011
--usage:
--this is a function, which means it can be on the right-hand side
--of an assignment. It returns a mean-zero random number from a
--normal distribution. The argument is a real number that indicates
--the standard deviation desired.
--
--random_noise(sigma);
--

package normal_distribution_random_noise is

function random_noise (
sigma : real)
return real;

end package normal_distribution_random_noise;

package body normal_distribution_random_noise is

function random_noise (
sigma : real
)
return real is

--variables
variable u_noise: real; --uniform distribution noise
variable n_noise: real := 0.0; --normal distribution noise
variable seed1 : positive;
variable seed2 : positive;

begin

--obtain a uniformly distributed random number
uniform(seed1, seed2, u_noise);
--report "Random uniform noise is " & real'image(u_noise) & ".";

for normal_count in 0 to 12 loop
--Turn the uniform distributed number
--into a normally distributed number
--by using the central limit theorem.
--Make it mean zero and make it have
--the range of the uniform numbers
--that it is composed from.
n_noise := n_noise + u_noise;
end loop;

n_noise := n_noise - (0.5)*(real(12)); --normal distribution with a mean
of zero
--report "Random normal noise is " & real'image(n_noise) & ".";
n_noise := n_noise/(real(12));
--report "Random normal noise using range of uniform is " &
real'image(n_noise) & ".";
n_noise := sigma*n_noise;

return n_noise;
end function random_noise;
end package body normal_distribution_random_noise;