VHDL entity for the IQ Gain and Phase Correction algorithm (Tuesday Challenge!)

entity IQGainPhaseCorrection is

generic(input_width:natural:=7;
output_width:natural:=7);

port(
x1:in bit_vector(input_width downto 0);
y1:in bit_vector(input_width downto 0);
gain_error:out bit_vector(output_width downto 0);
phase_error:out bit_vector(output_width downto 0)
);

end IQGainPhaseCorrection;

Hi Everyone,

Here's the entity:

--------------------------
entity IQGainPhaseCorrection is

generic(input_width:natural:=7;
output_width:natural:=7);

port(
x1:in bit_vector(input_width downto 0);
y1:in bit_vector(input_width downto 0);
gain_error:out bit_vector(output_width downto 0);
phase_error:out bit_vector(output_width downto 0)
);

end IQGainPhaseCorrection;
--------------------------

An entity in VHDL is the interface to the outside world. It's equivalent to the
list of pins of an IC that you might want to use in a project.

Here, there are two inputs, the I and Q signals, and two outputs, the gain error
and the phase error between the two signals, so that the errors can be
corrected.

The "generic" keyword allows parameters in VHDL to be set. You can see that
there's an input width and an output width. It allows flexibility and reuse in
VHDL.

My question: Is 8-bit widths for both reasonable?