PRNG seems to work

In the absence of thoroughly testing it, I can't state definitively that it is a wholly successful implementation, but the MEP "yet another pseudorandom number generator" VHDL module appears to work. Source code included below.
 
-Michelle W5NYV
 
 
----------------------------------------------------------------------------------
-- Company: Optimized Tomfoolery
-- Engineer: Michelle Thompson
--
-- Create Date:    16:34:20 05/28/2010
-- Design Name: BERT
-- Module Name:    PRNG - Behavioral
-- Project Name: MEP
-- Target Devices:
-- Tool versions:
-- Description: Pseudorandom Number Generator for Bit Error Rate Tester
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity PRNG is
    Port ( prn_out : out  BIT_VECTOR (7 downto 0);
           initial_value : in  BIT_VECTOR (7 downto 0));

 --declare signals here
 --clock
  signal Tic_Toc : STD_LOGIC := '0';
 --set signals
  signal Set0 : STD_LOGIC := '0';
  signal Set1 : STD_LOGIC := '0';
  signal Set2 : STD_LOGIC := '0';
  signal Set3 : STD_LOGIC := '0';
  signal Set4 : STD_LOGIC := '0';
  signal Set5 : STD_LOGIC := '0';
  signal Set6 : STD_LOGIC := '0';
  signal Set7 : STD_LOGIC := '1';  
 --reset signals
  signal Reset0 : STD_LOGIC := '0';
  signal Reset1 : STD_LOGIC := '0';
  signal Reset2 : STD_LOGIC := '0';
  signal Reset3 : STD_LOGIC := '0';
  signal Reset4 : STD_LOGIC := '0';
  signal Reset5 : STD_LOGIC := '0';
  signal Reset6 : STD_LOGIC := '0';
  signal Reset7 : STD_LOGIC := '0';  
 --results signals
  signal R7 : BIT := '0';
  signal R6 : BIT := '0';
  signal R5 : BIT := '0';
  signal R4 : BIT := '0';
  signal R3 : BIT := '0';
  signal R2 : BIT := '0';
  signal R1 : BIT := '0';
  signal R0 : BIT := '0';
 --feedback signals
  signal F3 : BIT := '0';
  signal F2 : BIT := '0';
  signal F1 : BIT := '0';
  signal F0 : BIT := '0';
    
end PRNG;
 
architecture Behavioral of PRNG is
--clock source
 component clock
  generic (PULSE_WIDTH : TIME);
  port (clock: out STD_LOGIC);
 end component;
 
 
--d flip flop component
 component d_flip_flop
  port (data_in: in BIT;
    clock: in STD_LOGIC;
    data_out: out BIT;
    set: in STD_LOGIC;
    reset: in STD_LOGIC);
 end component;

--xor gate component
 component exor
  port ( xor_data_in_a : in  BIT;
     xor_data_in_b : in  BIT;
     xor_data_out  : out  BIT);
 end component;

begin
 Set7 <= '0' after 10 ns;

 Synch: clock
  generic map (PULSE_WIDTH => 5 ns)
  port map (Tic_Toc);
  
 Do_xor_01: exor
  port map (F0, R2, F1);
  
 Do_xor_02: exor
  port map (F1, R3, F2);
  
 Do_xor_03: exor
  port map (F2, R7, F3);
 
 Drive_Flip_Flop_0: d_flip_flop
  port map (R1, Tic_Toc, R0, Set0, Reset0);
  
 Drive_Flip_Flop_1: d_flip_flop
  port map (R2, Tic_Toc, R1, Set1, Reset1);
  
 Drive_Flip_Flop_2: d_flip_flop
  port map (R3, Tic_Toc, R2, Set2, Reset2);
 Drive_Flip_Flop_3: d_flip_flop
  port map (R4, Tic_Toc, R3, Set3, Reset3);
 Drive_Flip_Flop_4: d_flip_flop
  port map (R5, Tic_Toc, R4, Set4, Reset4);
 Drive_Flip_Flop_5: d_flip_flop
  port map (R6, Tic_Toc, R5, Set5, Reset5);
 Drive_Flip_Flop_6: d_flip_flop
  port map (R7, Tic_Toc, R6, Set6, Reset6);
 Drive_Flip_Flop_7: d_flip_flop
  port map (F3, Tic_Toc, R7, Set7, Reset7);
end Behavioral;

D flip flop tested, seems to work, next steps

I wrote another two VHDL modules in the effort to test the D flip flop code. I wrote an inverter in order to have an external inverter component and get some practice with incorporating components into architectures. I also wrote an architecture module. An architecture is a collection of components linked by signals. The architecture code is at the bottom of this email. Essentially, an architecture is a circuit. The components can be thought of as devices or ICs.

So, it seems to work. The flip flop is hooked up in a way that the inverted output is fed back in to its own input. This creates a divide by two counter, and that is indeed what happens in the simulator.

What are the flip flops for? They are the building blocks of the bit error rate tester, which will be implemented in an FPGA and will be used to measure the performance of the receiver.

While this isn't bad for a beginner, and while the layout of a bit error rate tester is straightforward, the strategy for the actual receiver is not as clear-cut. I have a growing competence with what a Costas Loop does, and it's starting to make some sense, but the identification of individual modules is going to probably proceed pretty much like this effort, with the individual components being built up from very simple starting points.

Next steps:
1) Work on the website to better archive/present/share/explain the VHDL
2) Put the flip flops together to make a pseudorandom number generator and test it.

Here's the code:
----------------------------------------------------------------------------------
-- Company: Optimized Tomfoolery 
-- Engineer: Michelle Thompson
--
-- Create Date:    10:53:22 05/28/2010
-- Design Name: BERT
-- Module Name:    test_flip_flop - Behavioral
-- Project Name: MEP
-- Target Devices:
-- Tool versions:
-- Description: hook up flip flop and clock and see if it works
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_flip_flop is
 --declare signals here
 signal Tic_Toc : STD_LOGIC := '0';
 signal Output_Data : BIT := '0';
 signal Output_Data_Inverted : BIT := '0';
 signal Set : STD_LOGIC := '0';
 signal Reset : STD_LOGIC := '0';
end test_flip_flop;

architecture Behavioral of test_flip_flop is
 component clock
  generic (PULSE_WIDTH : TIME);
  port (clock: out STD_LOGIC);
 end component;
 
 component d_flip_flop
  port (data_in: in BIT;
    clock: in STD_LOGIC;
    data_out: out BIT;
    set: in STD_LOGIC;
    reset: in STD_LOGIC);
 end component;
 
 component inverter
  port (inverter_data_in: in BIT;
    inverter_data_out: out BIT);
 end component;
 

begin
 Synch: clock
  generic map (PULSE_WIDTH => 50 ns)
  port map (Tic_Toc);
  
 Invert: inverter
  port map (Output_Data, Output_Data_Inverted);
 
 Drive_Flip_Flop: d_flip_flop
  port map (Output_Data_Inverted, Tic_Toc, Output_Data, Set, Reset);
end Behavioral;
----------------------------------------------------------------------------------

and now... a clock!

In order to drive the flip flop, a clock was coded up in VHDL. Here's the code below.

The clock period is set with a local variable called PULSE_WIDTH.

Again, very simple and basic, but making progress.

We've been studying a book by U. Meyer-Baese called "Digital Signal Processing with Field Programmable Gate Arrays". There's a section on Costas Loops that reiterates what Bob McGwier said about phase and gain sensitivity. So, we're on the right track!

We'll most likely start storing these files on the website. Another place they will live, as a project, will be at the Open Cores website, where lots of open source HDL projects are hosted.

----------------------------------------------------------------------------------
-- Company: Optimized Tomfoolery
-- Engineer: Michelle Thompson
--
-- Create Date:    09:40:09 05/27/2010
-- Design Name: BERT
-- Module Name:    clock - Behavioral
-- Project Name: MEP
-- Target Devices:
-- Tool versions:
-- Description: Clock that drives d flip flop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock is
 generic (PULSE_WIDTH : TIME := 20ns);
    Port ( clock : out  STD_LOGIC);
end clock;
architecture Behavioral of clock is
begin
 Gen_Clock:
 process
  constant PERIOD: TIME := 2*PULSE_WIDTH;
 begin
  clock <= '1' after PULSE_WIDTH,
     '0' after PERIOD;
  wait for PERIOD;
 end process Gen_Clock;
end Behavioral;
----------------------------------------------------------------------------------

more soon, 
-Michelle W5NYV
Potestatem obscuri lateris nescis.

d flip flop synthesized

After some reading and some learning, I was able to synthesize a D flip flop in VHDL using Xilinx ISE (webpack version 11).

It's a small step, but it's a building block for a pseudorandom number generator that will be used in the bit error rate tester. This tester (BERT for short) will be used as a tool to test the MEP receiver.

It's such a short bit of code so far that I'm going to include it in this email in its entirety!   :+)    
 
Here it is:

----------------------------------------------------------------------------------
-- Company: Optimized Tomfoolery
-- Engineer: Michelle Thompson
--
-- Create Date:    08:32:51 05/26/2010
-- Design Name: Bit Error Rate Tester
-- Module Name:    d_flip_flop - Behavioral
-- Project Name: MEP
-- Target Devices:
-- Tool versions:
-- Description: A bit error rate tester for MEP receiver
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity d_flip_flop is
    Port ( data_in : in  STD_LOGIC;
           clock : in  STD_LOGIC;
           data_out : out  STD_LOGIC;
           set : in  STD_LOGIC;
           reset : in  STD_LOGIC);
end d_flip_flop;

architecture Behavioral of d_flip_flop is
begin
 process (data_in, clock, set, reset)
 begin
 -- asynchronous reset output to 0
 if (reset = '1')
 then data_out <= '0';
  -- asynchronous set output to 1
  elsif (set = '1')
  then data_out <= '1';
  
  --clock rising edge
   elsif(clock='1' and clock'event)
   then data_out <= data_in;
 end if;
 end process;
end Behavioral;
----------------------------------------------------------------------------------

Next step is to document in a way that makes it easier to participate. Then, add code that makes the inputs wiggle so that the outputs wiggle. Then, test to make sure it behaves exactly as a D flip flop should. This will be the first component in the MEP VHDL library of parts that will make up the tools and pieces of the system.

More soon!
-Michelle W5NYV

Potestatem obscuri lateris nescis.

Update to MEP costas loop RX, FPGA virtual conference

Latest sketch attached!

End of school year here at my household, so have been a busy bee for the past few weeks.

There is a "virtual conference" coming up for FPGAs. Check out http://www.eetimes.com/FPGA/ for more details.
-Michelle W5NYV